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My last IC design at Intel was a Graphics Chip and I developed a layout generator for Programmable Logic Arrays (PLA) that automated the task, so I’ve always been interested in how to make IC layout more push-button and less polygon pushing. Today I watched a video about HiPer DevGen from Tanner EDA and wanted to share what I … Read More
MONROVIA, California – December 7, 2010 – With pressure to reduce time to market and with resources increasingly constrained, tools that can enable maximum productivity for analog and mixed-signal design are mission-critical. Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal… Read More
