From Simulink to High-Quality RTL using High-Level Synthesis — The Design Methodology
Register For This Web Seminar
Online – Jul 14, 2020
10:00 AM – 11:00 AM US/Pacific
10:00 AM – 11:00 AM US/Pacific
Overview
Nowadays many ASIC and FPGA design projects start with a Simulink reference model. The traditional path from an abstract floating-point Simulink model to high-quality RTL code is long and often requires multiple