Getting More Productive Coding with SystemVerilog

Getting More Productive Coding with SystemVerilog
by Daniel Payne on 08-31-2017 at 12:00 pm

HDL languages are a matter of engineering personal preference and often corporate policy dictates which language you should be using on your next SoC design. In the early days we used our favorite text-based editor like Vi or Emacs, my choice was Vi. The problem with these text-based editors of course is that they really don’t… Read More