Connecting the Dots: Why RISC-V System Design Is Entering a New Era

Connecting the Dots: Why RISC-V System Design Is Entering a New Era
by Kalar Rajendiran on 05-04-2026 at 10:00 am

Andes x Arteris Pre Verified and Silicon Proven SoC Integration

At the recent RISC-V Now event hosted by Andes, the discussion underscored the fact that RISC-V is no longer just about instruction set architecture advantages or customizable cores. The real focus has moved up the stack to system-level design. This is where connectivity, integration, and security define whether an innovation… Read More


Podcast EP287: Advancing Hardware Security Verification and Assurance with Andreas Kuehlmann

Podcast EP287: Advancing Hardware Security Verification and Assurance with Andreas Kuehlmann
by Daniel Nenni on 05-16-2025 at 10:00 am

Dan is joined by Dr. Andreas Kuehlmann, Executive Chairman and CEO at Cycuity. He has spent his career across the fields of semiconductor design, software development, and cybersecurity. Prior to joining Cycuity, he helped build a market-leading software security business as head of engineering at Coverity which was acquired… Read More


Webinar on Detecting Security Vulnerabilities in SoCs

Webinar on Detecting Security Vulnerabilities in SoCs
by Tom Simon on 04-06-2020 at 10:00 am

Secure development Lifecycle for SOCs

As more security related capabilities are added in hardware it is changing the effort required to ensure that SoCs are not prone to attack. Hardware has the initial appeal of creating physical barriers to attack, yet it presents its own difficulties. For one thing, a flaw in a hardware security feature is much harder to fix in the … Read More