Tag: full-chip

CadenceTECHTALK: Cadence Certus | Delivering Overnight Concurrent Full-chip Optimization and Signoff

CadenceTECHTALK: Cadence Certus | Delivering Overnight Concurrent Full-chip Optimization and Signoff
by Admin on 01-16-2023 at 2:15 pm

Date: 2023 .02. 17 (Thursday)

Time: 14:00pm – 15:00pm (Taipei Time)

Wondering how to accelerate your design closure?

The Cadence Certus Closure Solution is the industry’s first fully automated and massively distributed environment for full-chip optimization and signoff. It delivers up to 10X concurrent chip-level

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Accelerate Full-Chip Signoff with Massively Parallel Scalability

Accelerate Full-Chip Signoff with Massively Parallel Scalability
by Admin on 05-17-2021 at 12:06 pm

Overview

Physical design constraints become a lot more complicated in the advanced nodes, leading to the exponential growth of design rules while adding complexity. Decreasing the active device sizes and higher geometry densities results in increased design rule check (DRC) run time, a big metal fill impact on chip functionality,

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