Curvilinear FPD Layout and Schematics

Curvilinear FPD Layout and Schematics
by Daniel Payne on 12-03-2020 at 10:00 am

layout ladder min

You are likely reading this blog using a Flat Panel Display (FPD), because they are so ubiquitous in our desktop, tablet and smart phone devices. Today I’m following up from a previous article. A quick recap of the unique design flow for FPD is shown below:

What follows is the second part of a Q&A discussion with Chen Zhao… Read More


Viewing the Largest IC Layout Files Quickly

Viewing the Largest IC Layout Files Quickly
by Daniel Payne on 03-10-2020 at 6:00 am

Skipper, Empyrean

The old adage, “Time is money”, certainly rings true today for IC designers, so the entire EDA industry has focused on this challenging goal of making tools that help speed up design and physical verification tasks like DRC (Design Rule Checks) and LVS (Layout Versus Schematic). Sure, the big three EDA vendors have… Read More


Speeding up Circuit Simulation using a GPU Approach

Speeding up Circuit Simulation using a GPU Approach
by Daniel Payne on 08-22-2019 at 10:00 am

ALPS-GT

The old adage that “Time is Money” certainly rings true in the semiconductor world where IC designers are being challenged with getting their new designs to market quickly, and correctly in the first spin of silicon. Circuit designers work at the transistor-level, and circuit simulation is one of the most time-consuming… Read More


WEBINAR: GPU-Powered SPICE – The Way Forward for Analog Simulation

WEBINAR: GPU-Powered SPICE – The Way Forward for Analog Simulation
by Randy Smith on 07-10-2019 at 9:37 am

Several years ago, I was a consultant to a company called Gauda, Inc.  I enjoyed working with Gauda as the technology was interesting. On June 3, 2014, Gauda, Inc. was acquired by D2S, Inc. so their technology lives on. Gauda was focused on optical proximity correction (OPC) and optical proximity verification solutions utilizing… Read More