Array
(
[content] =>
[params] => Array
(
[0] => /forum/whats-new/latest-activity?before_id=111713
)
[addOns] => Array
(
[DL6/MLTP] => 13
[Hampel/TimeZoneDebug] => 1000070
[SV/ChangePostDate] => 2010200
[SemiWiki/Newsletter] => 1000010
[SemiWiki/WPMenu] => 1000010
[SemiWiki/XPressExtend] => 1000010
[ThemeHouse/XLink] => 1000970
[ThemeHouse/XPress] => 1010570
[XF] => 2031070
[XFI] => 1060170
)
[wordpress] => /var/www/html
)
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The 3D DRAM in principle reduces the rowhammer risk with larger separations between word lines, but the JEDEC standard of 32 ms may be...
May 3, 2026
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The scaling will be most strongly impacted by distances within the DRAM cell itself. The VCT 4F2 architecture is motivated by the bit...
May 3, 2026
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For DDR5/LPDDR5, refresh rate doubled from every 64 ms to every 32 ms. I'm pretty sure rowhammer had a lot to do with it. So this...
May 3, 2026
F
In the vein of "Ask the Experts" --
I understand that denser DRAM spends more time refreshing than 'less dense DRAM', in terms of...
May 3, 2026
C
It isn't the long pole in the DRAM scaling equation but it's certainly an important consideration. Embedded DRAM (IBM) was/is big with...
May 3, 2026
The move widens TSMC’s lead over Samsung, as Intel also presses into the foundry market
TSMC increases 2nm and 3nm production by 20%...
May 3, 2026
I think that Intel spent much of its history depending heavily on having a better process available to their designs .... sometimes...
May 3, 2026
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Author: Su Ziyun | Publication Date: April 16, 2026, 12:13 PM
According to Wccftech, Qualcomm is collaborating with Chinese memory...
May 2, 2026
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EUV tools and all the fabs’ land, buildings, and machines are part of Property, Plant, and Equipment (PP&E) in accounting. Here I...
May 2, 2026
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I think that Intel spent much of its history depending heavily on having a better process available to their designs .... sometimes...
May 2, 2026
J
Sam's 4nm node's density is somewhere between the density of TSMC's N6 and N5 based on what I saw on AI search.
May 2, 2026
K
RAM shortages aren't helping either.... not that I want to add insult to injury here ;).
May 2, 2026
O
I think that Intel spent much of its history depending heavily on having a better process available to their designs .... sometimes...
May 2, 2026
O
Yes, even the new 13A is still low NA EUV
May 2, 2026
O
RAM shortages aren't helping either.... not that I want to add insult to injury here ;).
May 2, 2026
Like.
In the vein of "Ask the Experts" -- I understand that denser DRAM spends more time refreshing than 'less dense DRAM', in terms of...
user nl reacted to Daniel Nenni's post in the thread TSMC Widens Gap with Samsung by Expanding 2nm and 3nm Output by 20% with