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P
TSMC got to the first place by always being the largest, mass market, most volume oriented foundry. In the last few years, they were...
Feb 21, 2026
P
I think it's not wise to take what "cryptoentrepreneurs" talk seriously
Feb 21, 2026
P
I hear roar from Dongguan
Chinese factory owners are not afraid of tariffs as such, as the chance that money streams will switch to...
Feb 21, 2026
Future Intel iGPUs, NPU (AI) type dies are possible candidates for 18A HD as they don't need to aim for maximum clock rates.
Feb 21, 2026
Well NVL is mix of 18AP/N2for compute tiles
I remember the issue being parametric not the D0 the D0 has been decent from what i know
Feb 21, 2026
I mean, if 18A can achieve the same level of performance/pc with less manufacturing complexity, it should be a competititve alternative
Feb 21, 2026
yeah smaller dimensions are more work especially 32nm single print
Feb 21, 2026
I would like to point out few things
- Intel has traditionally used HP Cells in their Products. Intel 10nm -> ADL,RPL,TGL Intel 4/3 ->...
Feb 21, 2026
Some key Panther Lake design rules were posted on X:
Minimum pitch 36 nm (7nm-class), density obviously helped by 5 tracks from...
Feb 21, 2026
S
Well NVL is mix of 18AP/N2for compute tiles
I remember the issue being parametric not the D0 the D0 has been decent from what i know
Feb 21, 2026
M
Sam now says OpenAI's spend will be $600B, not $1.4T anymore. What do you think, is this reset expected, or a huge nasty surprise?
Key...
Feb 21, 2026
M
Tariffs was like 3 or 4 crises ago, they served their purpose for insider trading and now we can move on to the next charade.
Feb 21, 2026
L
I think the article want to point out that even under HP cell the yield is still not high, so the HD cell with smaller pitch may get...
Feb 21, 2026
F
If Backside or GAA/RibbonFET are new sources of yield loss, then relaxing to 36 nm pitch looks understandable. That said, high defect...
Feb 21, 2026
Xebec replied to the thread Panther Lake design rules revealed, no HD cells.Future Intel iGPUs, NPU (AI) type dies are possible candidates for 18A HD as they don't need to aim for maximum clock rates.
Like.
Well NVL is mix of 18AP/N2for compute tiles I remember the issue being parametric not the D0 the D0 has been decent from what i know