Array
(
[content] =>
[params] => Array
(
[0] => /forum/whats-new/latest-activity?before_id=103243
)
[addOns] => Array
(
[DL6/MLTP] => 13
[Hampel/TimeZoneDebug] => 1000070
[SV/ChangePostDate] => 2010200
[SemiWiki/Newsletter] => 1000010
[SemiWiki/WPMenu] => 1000010
[SemiWiki/XPressExtend] => 1000010
[ThemeHouse/XLink] => 1000970
[ThemeHouse/XPress] => 1010570
[XF] => 2030970
[XFI] => 1060170
)
[wordpress] => /var/www/html
)
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Hard to believe AMD would give up first class flying at TSMC. They can make wafers at TSMC in AZ all day long. I bet TSMC AZ will double...
Dec 14, 2025
Mustafa Suleyman, chief executive officer of Microsoft AI, speaks during an event commemorating the 50th anniversary of the company at...
Dec 14, 2025
P
A sheet with core sizes of CPU Cores
https://docs.google.com/spreadsheets/d/1r_RGcH02hcM2p-UYIbJFBJ_vJYrwtdC7w1dWXda0iwI/edit?gid=0#gid=0
Dec 14, 2025
S
siliconbruh999 replied to the thread
PAX SILICA .
You missed Intel/Micron/TI/GF
Dec 13, 2025
S
first thing requires reverse engineering and second thing i have seen a source for it but it's only for fewer comparison
Dec 13, 2025
F
Actually TSMC N7 to N5 M2 pitch shrink (40 nm to 35 nm) wasn't enough by itself to justify a node change. Gate pitch shrink was also...
Dec 13, 2025
F
TSMC N6 changed diffusion break from double to single, that in itself is enough to put it above 100 MTr/mm2. So it is a noticeable jump...
Dec 13, 2025
L
It seems like N+3 is truly G57H228 ( come from Techinsight decap data).
Hard to judge whether this is 5nm or not.
Techinsight think...
Dec 13, 2025
K
Great list - would be interesting to look at number of transistors and rough power / performance curve of each core.
Dec 13, 2025
A sheet with core sizes of CPU Cores
https://docs.google.com/spreadsheets/d/1r_RGcH02hcM2p-UYIbJFBJ_vJYrwtdC7w1dWXda0iwI/edit?gid=0#gid=0
Dec 13, 2025
D
N2 elvt threhold is around 0.1v.
The real trick is leakage.
Most btc mining chips are using dynamic logic which are almost impossible...
Dec 13, 2025
You heard it here first: AMD $AMD is planning to use Intel $INTC foundry to manufacture chips in the USA (not just packaging). During my...
Dec 13, 2025
Daniel Nenni replied to the thread
PAX SILICA .
What is Pax Silica?
We affirm our shared commitment to advance mutual prosperity, technological progress, and economic security for...
Dec 13, 2025
S
interesting. i thought bit mining is mainly performance driven. Lowering vdd to 0.25v using existing leading edge means they are all...
Dec 13, 2025
S
BTC mining chips .
TSMC N3P and N2.
Dec 13, 2025