The day of March 25th was an interesting one. At an IEEE conference, Huawei presented a paper and a set of slides on what it thinks is its next era of compute. With limited access to logic scaling, it is broadening the field, which makes sense. However, they also claim to jump ahead of everyone else in the world on few key metrics, and start calculating transistor density wrong, before we even saw that the research paper is written with AI.
There are questions to answer.
[00:00] Huawei 14A scaling overview
[00:14] Introduction to Tau Scaling [00:44] LogicFolding architecture concepts
[02:18] Huawei 14A density targets
[03:09] Tau Scaling physics principles
[09:21] LogicFolding interconnect mechanics
[10:48] AI academic writing patterns
[11:16] Stacking thermal management challenges
[15:24] Sub-micron LogicFolding specifications
[23:44] Huawei 14A density metrics
[33:16] 3D logic thermal limitations
[38:43] HBM logic stacking research
[43:05] Advanced bonding process yield
There are questions to answer.
[00:00] Huawei 14A scaling overview
[00:14] Introduction to Tau Scaling [00:44] LogicFolding architecture concepts
[02:18] Huawei 14A density targets
[03:09] Tau Scaling physics principles
[09:21] LogicFolding interconnect mechanics
[10:48] AI academic writing patterns
[11:16] Stacking thermal management challenges
[15:24] Sub-micron LogicFolding specifications
[23:44] Huawei 14A density metrics
[33:16] 3D logic thermal limitations
[38:43] HBM logic stacking research
[43:05] Advanced bonding process yield
