Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/threads/saqp-cost-reduction.8645/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021770
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

SAQP cost reduction

Fred Chen

Moderator
SAQP cost reduction: cut redistribution and 2D grid-based SAQP

Self-aligned quadruple patterning (SAQP) is the most likely technique to be applied to pattern pitches from 40 nm down to 20 nm.

SAQP involves the use of two rounds of spacer-based patterning, each time halving the pitch. Most commonly the second spacers define the features themselves. When the features are conducting it is necessary to cut the loops. It is desirable to reduce the number of cutting steps and their associated masks.

One approach recently considered has been cut relocation, mentioned in Wikipedia: File:SAQP Dense Cut Metal Optimization.png - Wikipedia
View attachment 20897
In essence, the cut locations are moved around so that they do not have to be separately patterned. An etch shrink separation is mentioned in the references to achieve tighter pitch than 80 nm (for immersion litho); without this, instead of reducing to one cut mask in the above picture, there would be two, which is still better than four.

Toshiba had also published in 2015 (F. Nakajima et al., Proc. SPIE 9427, 942708) a grid-based SAQP scheme, also using three feature colors, but not so explicitly dependent on pinching to separate features: File:SAQP by Toshiba.png - Wikipedia
View attachment 20698
A single cut mask by immersion litho is once again entirely reasonable. However, the trend seems to have evolved toward more 1D patterns, which results in more cut points being inserted along a line, and this tends to proliferate the number of cut masks needed.
 
Last edited:
Self-aligned blocking (SPIE 2017)

Last year, it had appeared SAQP (for logic/foundry) for BEOL would be coming soon, but now it still seems quite remote (BEOL is still mostly SADP), which may not be a bad thing. In the meantime, the latest serious attempt at SAQP cost reduction, which also has quite strong vendor (i.e., TEL) support, is self-aligned blocking (SAB). It was described at 2017 Advanced Lithography (paper 1014704: N. Mohanty et al., "EPE improvement thru self-alignment via multi-color material integration" (c) 2017 SPIE). The concept is simple yet sophisticated. After SAQP, the (second) spacers are hanging on the sidewall of the core lines, and a spin-on material is used to fill the remaining gaps between the spacers. The spin-on material and the core material have different etch selectivities. Thus, they may be cut independently. The picture below illustrates this:

File:Self-aligned_blocking.png

View attachment 20896(picture source: Wikipedia - Multiple patterning)

The core cut etch only etches the core lines without affecting the gap lines, while the gap cut etch only etches the gap lines, without affecting the core lines.

For BEOL metal patterning, where this is targeted, the cuts need to be tone-reversed by another spin-on material, while the core and gap areas are finally etched for pattern transfer. This arrangement results in the use of three masks total, whereas the regular approach easily uses four masks if not more. It is directly targeted for 20-30 nm metal pitches.

For the practically important case of SADP, the core lines may be patterned directly, avoiding the need for the core cut mask.

Back to the case of SAQP, one issue that strikes me as oddly unaddressed is the narrow cut of two adjacent metal lines at the same x- or y-coordinate; these lines would be opposite colors. Conventionally, one cut would suffice, but the two-color approach forces this to be two cuts. It seems for this approach to be worth it, every metal line segment must be sufficiently long, e.g., 60 nm. Or else, the two-line cut must be forbidden.

Given also that the minimum number of cut masks is two, it could be not as effective as the cut redistribution approach mentioned in the first post of this thread. But cut redistribution would have to restrict to cuts on multiple lines at the same coordinate, also a tall request.
 
Last edited:
Wire reordering

An old P&R technique could be all it takes for SAQP cost reduction. In SAQP, the metallization on a given layer consists of parallel wires; these may be reordered as needed for electrical targets, as well as for manufacturability; see http://www.eng.biu.ac.il/~wimers/files/journals/10-OptimalOrderingTiming.pdf for example. Intel recently noted the issue of multipatterning with significant number of mask exposures, as much as 6 on a layer, when announcing the latest 10nm delay. Checking the history, the earliest estimate was actually 4 cut masks, as below:

View attachment 21582
Each color in the above indicates a separate exposure. The lines were numbered to indicate the original order. By reordering the lines in a different sequence, the number of cut masks can be reduced to two:
View attachment 21583
The goal is to maximize "cut sharing" between adjacent lines (see the paper by Su and Chang below). If the next metal layer also has the similar wire ordering applied, the minimum cut pitch on the same wire could be avoided, so that, for example, the middle cut in the lowest wire above (wire 3) could be avoided. In that case, a reduction to a single cut mask is possible. Via locations are located next to cut locations, so they will benefit from the same reduction by reordering.

In addition to cut reduction, there are also some electrical benefits: http://www.aspdac.com/aspdac2017/archive/pdf/5C-4_add_file.pdf; also see the paper by Ewetz et al. below.

References:

Y-H. Su and Y-W. Chang, "Nanowire-Aware Routing Considering High Cut Mask Complexity," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, 964-977 (c) 2017 IEEE.

R. Ewetz, W-H. Liu, K-Y. Chao, T-C. Wang, and C-K. Koh, "A Study on the use of Parallel Wiring Techniques for Sub-20nm Designs, Proceedings of the 24th Great Lakes Symposium on VLSI, 129-134 (c) 2014 ACM.
 
Last edited:
Back
Top