Post Layout Simulation for Mixed Signal Design

[gp313]

Hi,

Recently I have verified the mixed-signal IP using UVM mixed signal environment (UVM-MS) through cadence virtuoso/spectre.
Now I want to do post layout simulation using this UVM environment. So, Is it possible?

If yes, then how to configure cadence environment and which extra files require for this post layout simulation.

Thanks
Gunjan Patel

 

[Daniel Payne]

Cadence has been talking about such a flow since 2012:

DVCon Paper: UVM-MS Brings Metric-Driven Verification to Mixed-Signal SoCs - Industry Insights - Cadence Blogs - Cadence Community

 

[gp313]

Hi Daniel,

This document contain how to set up the UVM-MS environment.
I have already UVM-MS environment.but I want to Post layout simulation using this environment.
I mean how to check DRC,LVS, parasitic extraction etc. I have already idea in GUI mode in cadence. but how to tool work in backend (script). if any command/ script available then help me. Through this I can easily set up the environment for post layout simulation.

 

[Daniel Payne]

This author may have some pointers:

Analog Mixed Signal Verification Methodology (AMSVM)

You may always contact your local Cadence AE for quickest assistance.