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Intel CEO Lip-Bu Tan stamps out chip bugs with aggressive new quality standards, says major validation errors can result in termination — 'B0, you keep your job. Anything above that, you are fired'
"One thing about timetable, I have a culture right now I have just implemented. It has to be A0 to production," said Lip-Bu Tan at JP Morgan's Global Technology, Media and Communications Conference. "A0 is when you tape out, first time pass. Intel does not have that culture, so I tell that, first time pass A0. B0, you keep your job. Anything above that, you are fired."
For relatively simple chips (compared to CPUs), A1 or A2 is often possible. For chips which use considerable state machine logic, B0 is aggressive, in my experience and from what I hear more recently from others. Just a guess... but chiplets must change the development norms a lot. Big dies with complex logic makes a B0 very aggressive. With chiplets, perhaps B0 is much more realistic.
For relatively simple chips (compared to CPUs), A1 or A2 is often possible. For chips which use considerable state machine logic, B0 is aggressive, in my experience and from what I hear more recently from others. Just a guess... but chiplets must change the development norms a lot. Big dies with complex logic makes a B0 very aggressive. With chiplets, perhaps B0 is much more realistic.
I'm curious how well or poorly the implementation of this is going to go. I can see bad responses like much longer time to (first) tape-out, or adding a lot more redundancy logic (die costs/size), or even performance missing targets (just remove a potentially buggy feature) to ensure A0 production.
I'm curious how well or poorly the implementation of this is going to go. I can see bad responses like much longer time to (first) tape-out, or adding a lot more redundancy logic (die costs/size), or even performance missing targets (just remove a potentially buggy feature) to ensure A0 production.
Your concerns are valid. A longer time to tape-out might not be such a bad thing, as long as milestone planning objectives are realistically extended. If not, dumb actions will result. I haven't ever seen cases of redundancy logic, except for adding cores to raise effective yields in production. But I was a development DoE who had to take over a project that unsuccessfully tried to avoid another letter stepping by disabling a performance feature which used state machines. Your concern is legitimate, IMO. My predecessor tried to remove the feature, and that caused other bugs which were not predicted, so I was appointed to fix the project. My answer, after an intensive design review - the letter stepping was required, and the feature had to be reinstated, or the result would be far worse. Let's just say my bad news delivery didn't enhance my Intel career path.
www.tomshardware.com
... The true no-win scenario.