This week at the IEEE Electronic Components and Packaging Technology Conference, Intel unveiled that it is developing new chip packaging technology that will allow for bigger processors for AI.
With Moore’s Law slowing down, makers of advanced GPUs and other data center chips are having to add more silicon area to their products to keep up with the relentless rise of AI’s computing needs. But the maximum size of a single silicon chip is fixed at around 800 square millimeters (with one exception), so they’ve had to turn to advanced packaging technologies that integrate multiple pieces of silicon in a way that lets them act like a single chip.
Three of the innovations Intel unveiled at ECTC were aimed at tackling limitations in just how much silicon you can squeeze into a single package and how big that package can be. They include improvements to the technology Intel uses to link adjacent silicon dies together, a more accurate method for bonding silicon to the package substrate, and system to expand the size of a critical part of the package that remove heat. Together, the technologies enable the integration of more than 10,000 square millimeters of silicon within a package that can be bigger than 21,000 mm2—a massive area about the size of four and a half credit cards.
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With Moore’s Law slowing down, makers of advanced GPUs and other data center chips are having to add more silicon area to their products to keep up with the relentless rise of AI’s computing needs. But the maximum size of a single silicon chip is fixed at around 800 square millimeters (with one exception), so they’ve had to turn to advanced packaging technologies that integrate multiple pieces of silicon in a way that lets them act like a single chip.
Three of the innovations Intel unveiled at ECTC were aimed at tackling limitations in just how much silicon you can squeeze into a single package and how big that package can be. They include improvements to the technology Intel uses to link adjacent silicon dies together, a more accurate method for bonding silicon to the package substrate, and system to expand the size of a critical part of the package that remove heat. Together, the technologies enable the integration of more than 10,000 square millimeters of silicon within a package that can be bigger than 21,000 mm2—a massive area about the size of four and a half credit cards.
Intel's Advanced Packaging for Bigger AI Chips
Intel's chip packaging R&D promise to enable massive silicon integration for AI. With Moore's Law slowing, could these advancements be the key to staying ahead in the AI race? #Intel #AI #ECTC #chippackaging
spectrum.ieee.org