Intel 14A pitches Rumour

[Fred Chen]

So in that case 20nm-24nm is not "green" for high-NA, contrary to what the slide suggests?

It was a measure of confidence against "variability risk", the "variability" not being stochastics, but process steps, e.g., overlay, feature tone reversal, etc..

 

[IanD]

It was a measure of confidence against "variability risk", the "variability" not being stochastics, but process steps, e.g., overlay, feature tone reversal, etc..

So it's deceptive to post it as if it shows a usability comparison between high-NA and SALELE low-NA, because it would lead people to draw the wrong conclusion about which nodes each can be used down to... :-(

(e.g. siliconbruh999 said "Intel says you don't need Double Patterning for 0.55NA 24nm pitch")

Is there a later slide from the same presentation that does include stochastics, as you described?

 

[Fred Chen]

So it's deceptive to post it as if it shows a usability comparison between high-NA and SALELE low-NA, because it would lead people to draw the wrong conclusion about which nodes each can be used down to... :-(

Is there a later slide from the same presentation that does include stochastics, as you described?

21 nm pitch

 

[Daniel Nenni]

Intel have had a pre-production tool since 2024.

That's not the same as having multiple production tools running on a production line with high throughput/yield/availability.

The whole point of high-NA -- at least, in the near future -- is to avoid having to use multiple-patterned EUV, on the grounds that this saves money (fewer masks/steps), increases throughput, and reduces TAT.

All of which are *economic* factors, not technical ones. I don't think there's any doubt that high-NA will work, the question is whether it's better than 0.33NA in mass production -- especially in *very* big volumes, which TSMC need.

So it might be better for (lower-volume) Intel than 0.33NA -- given that Intel are less obsessive about cost and yield than TSMC -- while not making sense for TSMC, at least not for a few years until it's been improved (higher throughput), the cost has come down, and machine availability has improved.

That certainly seems to be TSMCs view, and as the dominant foundry who really knows about mass-production of bleeding-edge processes it's difficult to argue with that -- they'll introduce it later when it makes business sense.

Whether Intel are correct remains to be seen, the high-NA position is more favourable for them given their volumes and priorities -- and anyway they have to be seen to do something different to TSMC like "having the most advanced technology" early (see also BSPD), otherwise they're just a smaller-volume higher-priced follower without the TSMC ecosystem... ;-)

TSMC notes from SPIE:

High-NA EUV remains challenged in yield as stochastic defect makes high-NA EUV linewidth roughness even harder to manage than low-NA double patterning. The TSMC roadmap shows the addition of 4th generation GAA node (A8) and a potential pushout of high-NA adoption beyond 2035

TSMC sees major process control challenges with the introduction of CFET at A7 and calls on the semicap industry to work on soft X-ray metrology, EUV ellipsometry, and hybrid metrology, which could be an inflection point that reshuffles the process control landscape.

 

[Daniel Nenni]

Someone leaked the pitch sizes for 14A on twitter
Intel 14A
Code: 1280
G48H126
M0: 28nm
Time: 2028

Intel 14A2
Code: 1280.1
G44H110
M0:21nm
Time: 2030

https://twitter.com/x/status/2067208021491798020

@Fred Chen @MKWVentures maybe you would find this interesting

FYI: I was told privately by a trusted source that these numbers are not correct. The correct numbers are under strict NDA which I will honor.

 

[Fred Chen]

The whole point of high-NA -- at least, in the near future -- is to avoid having to use multiple-patterned EUV, on the grounds that this saves money (fewer masks/steps), increases throughput, and reduces TAT.

One other important consideration for high NA is stitching. I don't think Intel can skirt around it. The High-NA scanner's throughput will depend on die/chiplet height even when stitching is not needed between parts of the chip. It's because of different numbers of row scans (2-3 shown below) to cover same common 26 mm x 33 mm field of the Low-NA or DUV.