GAINESVILLE, Fla., March 11, 2025 (GLOBE NEWSWIRE) -- The 2025 Design and Verification Conference and Exhibition U.S. (DVCon U.S.), sponsored by Accellera Systems Initiative (Accellera), concluded its 37th annual event in San Jose, CA earlier this month with record attendance since returning to an in-person event. The 2025 Stuart Sutherland Best Oral Presentation and Best Poster winners, as voted on by attendees, were announced during a reception in the exhibit hall on February 26.
Participants from 32 countries, representing approximately 350 companies, attended DVCon U.S. 2025, including 404 first-time attendees. The event featured 32 sponsors and exhibitors, six of whom were making their debut. Overall attendance reached approximately 1,067, including representatives from 26 exhibiting companies. The exhibit floor was sold out.
"DVCon U.S. 2025 was a tremendous success, bringing together the brightest minds in design and verification to explore the latest advancements in AI, formal verification, and industry standards,” stated Tom Fitzpatrick, DVCon U.S. 2025 General Chair. “With attendance reaching a new record since returning in-person, the enthusiasm and engagement from our attendees, speakers, and exhibitors showcased the vibrant innovation driving our industry forward. From thought-provoking keynotes to informative and educational technical sessions and a dynamic exhibition floor, this year’s conference reaffirmed DVCon’s role as the premier event for the design and verification community. We’re excited to be moving to a new venue in 2026, giving the conference room to grow and continue delivering an exceptional experience for our community."
The first-place award for the Stuart Sutherland Best Oral Presentation, as voted by conference attendees, was presented to Pritam Roy, Ping Yeung, Joon Hong, Abhishek Desai, Aishwarya Raj, Chirag Agarwal, and Dhruvin Patel from NVIDIA for their presentation, “Hierarchical Formal Verification and Progress Checking of Network-on-Chip Design.” Second-place honors went to Aman Kumar, Deepak Narayan Gadde, Keerthan Kopparam Radhakrishna, and Djones Lettnin from Infineon Technologies for their presentation, “Saarthi: The First AI Formal Verification Engineer.” Third place was awarded to Sam Mellor from Arm for “User Programmable Targeted UVM Debug Verbosity Escalation.”
Top honors for Best Poster went to Jonathan Bonsor-Matthews from LightBlue Logic Limited and Greg Law from Undo Limited for their poster, “Time-Travel Debugging for High-Level Synthesis Code.” Sean Little from Verus Research took second place for “A Survey of Predictor Implementation Using High-Level Language Co-Simulation.” Third place was awarded to Ahmed Allam from ICpedia for “Register Access by Intent: Towards Generative RAL-Based Algorithms.”
Highlights of the Week:
The proceedings from DVCon U.S. 2025 will be available to the public in June. To view proceedings from past conferences, visit the archives site.
About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., visit the DVCon U.S. website. Follow DVCon U.S. on Facebook, LinkedIn or X.
Link to Press Release
Participants from 32 countries, representing approximately 350 companies, attended DVCon U.S. 2025, including 404 first-time attendees. The event featured 32 sponsors and exhibitors, six of whom were making their debut. Overall attendance reached approximately 1,067, including representatives from 26 exhibiting companies. The exhibit floor was sold out.
"DVCon U.S. 2025 was a tremendous success, bringing together the brightest minds in design and verification to explore the latest advancements in AI, formal verification, and industry standards,” stated Tom Fitzpatrick, DVCon U.S. 2025 General Chair. “With attendance reaching a new record since returning in-person, the enthusiasm and engagement from our attendees, speakers, and exhibitors showcased the vibrant innovation driving our industry forward. From thought-provoking keynotes to informative and educational technical sessions and a dynamic exhibition floor, this year’s conference reaffirmed DVCon’s role as the premier event for the design and verification community. We’re excited to be moving to a new venue in 2026, giving the conference room to grow and continue delivering an exceptional experience for our community."
The first-place award for the Stuart Sutherland Best Oral Presentation, as voted by conference attendees, was presented to Pritam Roy, Ping Yeung, Joon Hong, Abhishek Desai, Aishwarya Raj, Chirag Agarwal, and Dhruvin Patel from NVIDIA for their presentation, “Hierarchical Formal Verification and Progress Checking of Network-on-Chip Design.” Second-place honors went to Aman Kumar, Deepak Narayan Gadde, Keerthan Kopparam Radhakrishna, and Djones Lettnin from Infineon Technologies for their presentation, “Saarthi: The First AI Formal Verification Engineer.” Third place was awarded to Sam Mellor from Arm for “User Programmable Targeted UVM Debug Verbosity Escalation.”
Top honors for Best Poster went to Jonathan Bonsor-Matthews from LightBlue Logic Limited and Greg Law from Undo Limited for their poster, “Time-Travel Debugging for High-Level Synthesis Code.” Sean Little from Verus Research took second place for “A Survey of Predictor Implementation Using High-Level Language Co-Simulation.” Third place was awarded to Ahmed Allam from ICpedia for “Register Access by Intent: Towards Generative RAL-Based Algorithms.”
Highlights of the Week:
- - The industry keynote on Tuesday, “AI Factories Drive Re-invention of Chip Design, Verification and Optimization,” was presented by Ravi Subramanian, Chief Product Management Officer at Synopsys and his guest, Artour Levin, Vice President of AI Silicon Engineering at Microsoft Corporation. The two discussed the challenges in the industry and opportunities for advancement. Subramanian declared, “We are at the dawn of the next industrial revolution. AI factories will define the landscape for the next decades, if not centuries.”
- - Wednesday morning kicked off with an insightful panel discussion: "Are AI Chips Harder to Verify?” Verification experts from across the industry explored the unique challenges of verifying AI-driven silicon. Panelists shared perspectives on how different business models impact verification strategies and emphasized the need for early stakeholder involvement when integrating AI into chip development. Most experts agreed that AI chips are 50% more difficult to verify due to their complexity and dynamic behaviors. However, they cautioned that AI is just one part of the solution to the industry's evolving challenges.
- - On Wednesday afternoon, Vivek Prasad, Vice President of Design Engineering EcoSystem Enablement, at Natcast, presented the invited keynote, “The Role of EDA in U.S. Economic Security.” His talk looked at the history of EDA and how it has enabled the semiconductor revolution, where it currently faces challenges, and how CHIPS for America and its CHIPS National Advanced Packaging Manufacturing Program is helping to address those challenges going forward.
- - The highly anticipated Poster Ninja Warrior Session once again highlighted the best in technical innovation, culminating in the selection of the Best Poster Award winners. For the third consecutive year, the top four poster presenters went head-to-head in a dynamic showdown, delivering their presentations in front of an engaged audience. Fielding questions from a panel of judges, the session was an exciting competition among colleagues.
The proceedings from DVCon U.S. 2025 will be available to the public in June. To view proceedings from past conferences, visit the archives site.
About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., visit the DVCon U.S. website. Follow DVCon U.S. on Facebook, LinkedIn or X.
Link to Press Release