The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical usage of specialized design and verification languages such as SystemC, SystemVerilog, assertions in SVA or PSL, as well as the use of AMS languages, design automation using IP-XACT and use of general purpose languages C and C++.
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Topic Area 1: System-Level Design
Call for Abstracts | DVCon
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Topic Area 1: System-Level Design
- Transaction level modeling for system-level design
- Hardware/software/embedded co-design
- System-on-Chip and Network-on-Chip design
- System-level design techniques, flows and methodologies
- High-level synthesis from ESL languages
- Virtual and Hardware (FPGA) prototyping
- Formal and semi-formal techniques
- Hardware/software co-verification
- Using multiple HDLs and/or HVLs in a design cycle
- Automated stimulus generation methods
- Advance methodologies and testbenches
- Verification process and resource management
- Tool and flow automation using IP-XACT
- SoC and IP integration methods and tools
- IP protection and security
- Configuration management of IP and abstraction levels
- Interoperability of models and/or tools
- Mixed-signal design and verification
- Real-value modeling approaches
- Application of mixed-signal extensions for UVM
- AMS system-level and concept design
- Low power design and verification
Call for Abstracts | DVCon
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