In June (2017) IBM introduced the 5-nm lithography node. Roadmaps for the semiconductor industry have requested that carrier profiling and dopant profiling each have a resolution finer than 10% of the dimension at each node. Atom Probe Tomography provides dopant profiling with atomic resolution. However, published data suggest that none of the present tools for carrier profiling have a resolution finer than 10-nm (20 times that requested for the 5-nm node). Generally carrier and dopant profiling are done together to provide complimentary information (e.g. What fraction of the dopant atoms is activated?).
A major and expensive effort in Extreme Ultraviolet lithography (EUV) is in progress for manufacturing at still finer lithography nodes but, without addressing the deficiency in carrier profiling, this is like trying to manufacture better cars without a micrometer. For example, the chip capacity in flash memory increased by 100-fold from 2005 to 2013 in accordance with Moore's Law [1]. However, the reliability of flash memory decreased at each step to a finer lithography so the reliable capacity actually stagnated during that period. One semiconductor metrologist told me that the need for improved carrier profiling was first evident at the 45-nm node. Additional data from the semiconductor industry would be appreciated to better define the extent of this problem.
Please respond by in-mail or via this thread with your suggestions or comments.
Reference:
1. A.A. Chien and V. Karamcheti, "Moore's Law: the first ending and a new beginning", Computer (IEEE) 46 (2013) 48-53.
A major and expensive effort in Extreme Ultraviolet lithography (EUV) is in progress for manufacturing at still finer lithography nodes but, without addressing the deficiency in carrier profiling, this is like trying to manufacture better cars without a micrometer. For example, the chip capacity in flash memory increased by 100-fold from 2005 to 2013 in accordance with Moore's Law [1]. However, the reliability of flash memory decreased at each step to a finer lithography so the reliable capacity actually stagnated during that period. One semiconductor metrologist told me that the need for improved carrier profiling was first evident at the 45-nm node. Additional data from the semiconductor industry would be appreciated to better define the extent of this problem.
Please respond by in-mail or via this thread with your suggestions or comments.
Reference:
1. A.A. Chien and V. Karamcheti, "Moore's Law: the first ending and a new beginning", Computer (IEEE) 46 (2013) 48-53.