Correct by construction IO timing solution

[jaweedali]

Hello Experts,

I'm researching a solution for correct by construction approach to solve block - block IO timing closure. Without the need to do traditional IO budgeting/prototyping, iterative constraints refining, etc..
Would appreciate any ideas/leads/references.

 

[Eoin McCann]

Hi there, I'll preface this by saying that I work for the company in question so there's a bit of self-help with this advice. Duolog have a product that has a correct-by-construction methodology for I/O design, it may be what you're looking for.

Here's the product page: Socrates Spinner | I/O Fabric Management | SoC (System on Chip) | Duolog Technologies

Let me know if this was what you were looking for

 

[jaweedali]

HI Eoin,

Thanks for the response, I guess you are referring to chip level IO pins. I'm looking for block-block IO pin timing solution.

Jaweed