Daniel Payne
Moderator
HLDVT'17 (October 5th – 6th, 2017)
http://www.ihldvt.com
The 19th IEEE International High-Level Design Validation and Test Workshop will be held at Hilton Santa Cruz, Santa Cruz, California, U.S.A., from October 5th – 6th, 2017.
You are invited to submit an abstract of your latest technical research in areas such as:
Simulation-Based Validation
Formal Verification, and Hybrid Methods
Design Abstraction, and Behavioral Modeling
Error Trace Interpretation, and Debugging
Functional safety/safety-critical system verification
On-Chip, and Core-Based Testing
Test Generation for Defects, Design Errors, and Delay Faults
Hardware/Software, and Mixed-Signal System Co-Validation
Emulation, and Prototyping
Post-silicon Validation, and Debug
Modeling, Simulation and Verification of Cyber-Physical Systems
Design and Test for AMS systems
Variability, Reliability and Dependability management of SoCs.
Abstracts due: July 14, 2017
Full papers due: July 23, 2017
http://www.ihldvt.com
The 19th IEEE International High-Level Design Validation and Test Workshop will be held at Hilton Santa Cruz, Santa Cruz, California, U.S.A., from October 5th – 6th, 2017.
You are invited to submit an abstract of your latest technical research in areas such as:
Simulation-Based Validation
Formal Verification, and Hybrid Methods
Design Abstraction, and Behavioral Modeling
Error Trace Interpretation, and Debugging
Functional safety/safety-critical system verification
On-Chip, and Core-Based Testing
Test Generation for Defects, Design Errors, and Delay Faults
Hardware/Software, and Mixed-Signal System Co-Validation
Emulation, and Prototyping
Post-silicon Validation, and Debug
Modeling, Simulation and Verification of Cyber-Physical Systems
Design and Test for AMS systems
Variability, Reliability and Dependability management of SoCs.
Abstracts due: July 14, 2017
Full papers due: July 23, 2017