Calculation of leakage current for a voltage value - memory bit cell

[Neil]

Hello,

I am looking for the mathematical formula for calculating leakage currents at the typical-typical and fast-fast corners for memory bit cells.
Any hints on what the equation is?

I am looking at 40nm and 28nm

 

[Daniel Payne]

One method is to create a transistor-level schematic, then an IC layout, extract the layout and create a SPICE netlist, then simulate the SPICE netlist and measure the leakage currents. This presumes that you have access to the PDK from the foundry for your 40nm and 28nm nodes.

 

[Neil]

Thanks Daniel. I am looking to compare the Ileakage for 40 and 28 ULP for a nominal vtg of 0.99V for both typical-typical and fast-fast. I am wondering what would be the best approach.

 

[Staf_Verhaegen]

Thanks Daniel. I am looking to compare the Ileakage for 40 and 28 ULP for a nominal vtg of 0.99V for both typical-typical and fast-fast. I am wondering what would be the best approach.

Some comments:

• I agree with Daniel that best way is to use foundry provided transistor models; due to short width and short length effects I don't see it possible to do it by formula's.
• As you already seem to have fixed the voltage I would not limit myself to the ULP version of a technology.
• Also temperature will be major contributor to leakage.
• Will you design own cell or use foundry or IP seller provided one ? Designing your own will mean much higher area as provided cell typically violates design rules. From the other side, provided cells don't allow optimization of L and W of transistors anymore for lowest leakage.

 

[Neil]

Thanks Staf, I will be using a foundry provided cell.