Press Highlights:
l Native support for BF16/FP16 for AI workloads
l Seamless NEON™ to RVV intrinsic support
l Unified High-bandwidth Vector Memory (HVM) management library
l Andes AutoOpTune™ AI-driven compiler optimization
l Enhanced trace support and debugging features
Hsinchu, Taiwan – June 09, 2025 – Andes Technology, the leading provider of high-performance, low-power RISC-V processor IP, today announced the release of AndeSight™ IDE v5.4. This latest version significantly accelerates AI and embedded software development by providing native support for key AI data types, unified High-bandwidth Vector Memory (HVM) management, seamless NEON™ to RVV intrinsic conversion, comprehensive trace analysis, and the innovative Andes AutoOpTune™ optimization tool.
The AndeSight™ v5.4 toolchain provides robust support for FP16 (Half-Precision Floating Point) and BF16 (Brain Floating Point), increasing performance and reducing memory bandwidth for AI workloads without compromising accuracy. A unified HVM management library simplifies high-speed, low-latency vector data access across Linux, RTOS, and bare metal platforms, significantly improving developer efficiency.
Additionally, the toolchain facilitates seamless migration between architectures by automatically converting ARM NEON™ intrinsics to RISC-V Vector (RVV) instructions. This capability allows developers to easily leverage Andes’ advanced vector processors for compute-intensive applications such as AI/ML inference and signal-processing tasks.
Further boosting developer productivity, AndeSight™ v5.4 introduces Andes AutoOpTune™, an AI-driven tool that automates compiler optimization targeting performance, code size, or balanced approaches. Developers gain actionable insights via detailed visualizations and reports, guiding informed optimization decisions tailored specifically to AndesCore™ processors.
The latest release also seamlessly integrates trace support into debugging features for both Uni-Processor (UP) and Symmetric Multi-Processor (SMP) RISC-V systems with new capabilities. The intuitive graphical interface now includes Eagle-Eye and Zoom-In views for traced code, enabling developers to efficiently capture, visualize, and analyze real-time execution flows. In addition to forward step into/over/return, timeline visualization, code coverage analysis, and performance profiling, users can now do backward step into/over/return on traced code. This dramatically accelerates debugging and reduces issue-resolution time.
“To fully exploit the potential of Andes RISC-V cores, an industry-strength, holistic software development suite must be able to integrate robust hardware, software, and ecosystem components seamlessly,” said Dr. Charlie Su, President and CTO of Andes Technology. “AndeSight™ IDE v5.4 provides critical capabilities, comprehensive trace features, optimized toolchains, compute libraries, and advanced automation via Andes AutoOpTune™, helping our customers rapidly develop differentiated, competitive products. Andes remains committed to strengthening the RISC-V software ecosystem, ensuring our community has access to the highest-performance RISC-V solutions.”
If you would like to learn more about AndeSight™ IDE v5.4, we warmly invite you to join the annual Andes RISC-V CON Hsinchu! The event will take place on June 10, from 1:30 PM to 5:00 PM at the Sheraton Hsinchu Hotel. We sincerely look forward to seeing you there!
About Andes Technology
As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 16 billion Andes-powered SoCs are driving innovations globally. Discover more at www.andestech.com and connect with Andes on LinkedIn, X, Bilibili and YouTube.
Link to Press Release
l Native support for BF16/FP16 for AI workloads
l Seamless NEON™ to RVV intrinsic support
l Unified High-bandwidth Vector Memory (HVM) management library
l Andes AutoOpTune™ AI-driven compiler optimization
l Enhanced trace support and debugging features
Hsinchu, Taiwan – June 09, 2025 – Andes Technology, the leading provider of high-performance, low-power RISC-V processor IP, today announced the release of AndeSight™ IDE v5.4. This latest version significantly accelerates AI and embedded software development by providing native support for key AI data types, unified High-bandwidth Vector Memory (HVM) management, seamless NEON™ to RVV intrinsic conversion, comprehensive trace analysis, and the innovative Andes AutoOpTune™ optimization tool.
The AndeSight™ v5.4 toolchain provides robust support for FP16 (Half-Precision Floating Point) and BF16 (Brain Floating Point), increasing performance and reducing memory bandwidth for AI workloads without compromising accuracy. A unified HVM management library simplifies high-speed, low-latency vector data access across Linux, RTOS, and bare metal platforms, significantly improving developer efficiency.
Additionally, the toolchain facilitates seamless migration between architectures by automatically converting ARM NEON™ intrinsics to RISC-V Vector (RVV) instructions. This capability allows developers to easily leverage Andes’ advanced vector processors for compute-intensive applications such as AI/ML inference and signal-processing tasks.
Further boosting developer productivity, AndeSight™ v5.4 introduces Andes AutoOpTune™, an AI-driven tool that automates compiler optimization targeting performance, code size, or balanced approaches. Developers gain actionable insights via detailed visualizations and reports, guiding informed optimization decisions tailored specifically to AndesCore™ processors.
The latest release also seamlessly integrates trace support into debugging features for both Uni-Processor (UP) and Symmetric Multi-Processor (SMP) RISC-V systems with new capabilities. The intuitive graphical interface now includes Eagle-Eye and Zoom-In views for traced code, enabling developers to efficiently capture, visualize, and analyze real-time execution flows. In addition to forward step into/over/return, timeline visualization, code coverage analysis, and performance profiling, users can now do backward step into/over/return on traced code. This dramatically accelerates debugging and reduces issue-resolution time.
“To fully exploit the potential of Andes RISC-V cores, an industry-strength, holistic software development suite must be able to integrate robust hardware, software, and ecosystem components seamlessly,” said Dr. Charlie Su, President and CTO of Andes Technology. “AndeSight™ IDE v5.4 provides critical capabilities, comprehensive trace features, optimized toolchains, compute libraries, and advanced automation via Andes AutoOpTune™, helping our customers rapidly develop differentiated, competitive products. Andes remains committed to strengthening the RISC-V software ecosystem, ensuring our community has access to the highest-performance RISC-V solutions.”
If you would like to learn more about AndeSight™ IDE v5.4, we warmly invite you to join the annual Andes RISC-V CON Hsinchu! The event will take place on June 10, from 1:30 PM to 5:00 PM at the Sheraton Hsinchu Hotel. We sincerely look forward to seeing you there!
About Andes Technology
As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 16 billion Andes-powered SoCs are driving innovations globally. Discover more at www.andestech.com and connect with Andes on LinkedIn, X, Bilibili and YouTube.
Link to Press Release