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Agree to disagree. TSMC's best customers are exclusive to TSMC and there are quite a few. Intel also competes with TSMC on the foundry side. Intel is certainly a big TSMC customer but I would not say best. Lip-Bu may change that, we shall see, but I can assure you CC Wei did not like Pat Gelsinger so some relationship repair must be done.
I still have not heard of an N2 wafer agreement with Intel but I will know more next week. In my opinion N3 will suffice for the supporting chiplets Intel will surround 18A die with. I am really hearing good things about 18A so in my opinion Intel will start moving away from TSMC in the very near future. Intel based N3 revenue however will have a long life, absolutely. TSMC N3 really is a record breaking node, absolutely.
As of rn Yes due to the N3B/E contracts but over time it's due to reduced I don't think anyone would like to keep wafers external while having internal wafer shop and loosing money on Internal wafer shop.
Intel is one of TSMCs top 6 customers in 2025 I believe
Intel external wafer sales are <1B per year in 2025. not a top 10 foundry in 2025
Intel 18A works very well from what I hear. The problem I am guessing is that the MOR output/tool is lower than expected, yields are not there yet (we are still 6 months from Product qual so not major) and as a result the 2026 product costs are higher than originally planned. So it might not be profitable in 2026.
If this were to be true (who knows). then the response would be to not ramp like planned. There are lots of Rock/hard place trade offs due to financing so we will see how it comes out in 2026. This will show how Tan's mind is thinking
Simple metric: in 2026 How many wafers are running on 18A, How many are being sold to Intel product group, How many to External foundry customer. Then ask IFS leader "what is the Operating Margin of the 18A product line" .... the answer will begin with "well, its complex and we have some unexpected ....."
I'm surprised. AMD was always slower moving to new TSMC nodes. Launching N2 products in 2026 alongside first Apple products is a big shift. And a welcome one, because I feel like their old strategy of not using TSMC's best was a disadvantaged strategy.
and you will not see any chiplets. This is a full N2 wafer. Chiplets use 2.5/3D integration techniques since chiplets are individual small chips that are used with interposers. Depending on how this N2 wafer was designed, the chiplets could be attached. But this N2 wafers has many individual (non chiplet) die that need to be scribed/broken from the whole wafer.
