Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/threads/how-collaboration-in-high-na-euv-and-transistor-r-d-are-shaping-future-waves-of-device-innovation.24204/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2030770
            [XFI] => 1060170
        )

    [wordpress] => /var/www/html
)

How Collaboration in High NA EUV and Transistor R&D Are Shaping Future Waves of Device Innovation

Daniel Nenni

Admin
Staff member
large



Semiconductor innovation has always been a team sport, with the most durable breakthroughs resulting from deep ecosystem collaboration starting in research and progressing to high volume manufacturing. Intel Foundry is proud of its leading role in this journey, establishing its place in the industry as the only American company with domestic leading-edge logic R&D and manufacturing capabilities.

Today we’re sharing milestones on two separate projects that illustrate different ways we’re driving industry research and innovation, de-risking advanced device concepts, and accelerating time to value for our customers.

Scaling with Confidence: First TWINSCAN EXE:5200B High NA EUV Installed​

As leading-edge process node feature dimensions continue to shrink, High Numerical Aperture (High NA) Extreme Ultraviolet (EUV) is quickly emerging as a compelling lithography capability for the AI era. ASML and Intel Foundry have demonstrated technical viability of the most advanced lithography scanner available in delivering improved accuracy and productivity that position High NA EUV for future high-volume manufacturing.

Specifically, today we are excited to share that Intel and ASML have reached the milestone of “acceptance testing” on the TWINSCAN EXE:5200B. This High NA EUV tool maintains the high resolution of the first-generation EXE:5000, while expanding output to 175 wafers per hour and improving overlay (accurate alignment of different lithography layers) to 0.7 nanometers. This builds on Intel’s experience with High NA EUV that began in 2023 with the shipment of the world’s first commercial High NA tool to our research and development fab in Oregon.

Key enabling innovations of the EXE:5200B include the following:
  • Higher power EUV source: Faster wafer exposure at practical doses, supporting resist/process windows for high contrast patterning while minimizing Line Edge Roughness and Line Width Roughness.

  • New wafer stocker architecture: Improved lot logistics and thermal/process stability, which mitigate drift and enhance throughput consistency, especially critical for multipass or multiexposure flows.

  • Tighter alignment control: The 0.7 nm overlay figure reflects advances in stage control, sensor calibration, and environmental isolation, all of which matter as customers push the limits of transistor density.
High NA EUV is an important capability in the Intel Foundry technology arsenal, combining our skills in related areas including masks, etch, resolution enhancement, and metrology to achieve the finer transistor details required for modern-day chips. The result for designers is more flexible design rules, and the ability to reduce steps and mask counts means a simplified process flow, better yields, and better time to yield. We’re still early on the journey, but this is positive progress in exploring new ways to increase efficiency and productivity for our customers.

2D Materials for Future Transistor Scaling​

We’re imagining even further into the future as well. Today’s most advanced transistors use a gate-all-around architecture, which Intel Foundry calls RibbonFET, to wrap the transistor completely around the channel. These transistors appear in a chip on a single layer, and we are also hard at work on enabling the stacking of transistors. We and others in the industry believe that at some point in the future, transistor dimensions will have scaled to a point where the silicon atoms start to lose their performance capabilities.

2D materials get their name for their ability to be arranged in a layer that is effectively a few atoms thick. These materials, for example in the family of transition-metal dichalcogenides or TMDs, promise exceptional ability to both scale and control the current. Intel Foundry and multiple partners have researched 2D materials for many years, but the industry still faces nontrivial barriers to manufacturability in a 300mm wafer fab.

In joint work presented at IEDM last week, Imec and Intel demonstrated a 300mm manufacturable integration of source/drain contacts and gate stack modules for 2DFETs (WS₂, MoS₂ for ntype; WSe₂ for ptype). The central innovation is a selective oxide etch applied to Intel-grown, high-quality 2D layers that were capped with AlOx/HfO₂/SiO₂. This enabled damascene-style top contacts, a reference to the ancient technique of embedding metal into a trench or groove. This is a world first for fab-compatible processing – while preserving the integrity of the underlying 2D channels.

For teams exploring 2DFETs, manufacturable contact and gate modules are among the largest challenges. By co-developing these steps and exposing them to production-class integration flows, our long-term plan is to work alongside customers to evaluate 2D channels with realistic, scalable process assumptions, accelerating device benchmarking, modeling, and design pathfinding with fewer surprises at tape in.

What does it all mean?​

First, disciplined integration converts novelty into reliability. Whether it’s new materials research or first-of-a-kind tools, the hardest work is aligning the physics and chemistry with a tool’s behavior in a high-volume fab. That’s the work that turns promising concepts into customer-ready platforms.

Second, open collaboration shortens learning curves. By codeveloping with esteemed organizations such as Imec and ASML, and by sharing process windows, metrology data, and failure modes, we accelerate innovation and reduce duplicated effort across the ecosystem. Customers benefit from faster ramps, improved PPAC, and earlier access to realistic design constraints.

Third and importantly, Intel Foundry focuses on manufacturability even from the early-research phase. The damascene-top-contact breakthrough was a materials win and a fab-compatible breakthrough. Likewise, the EXE:5200B installation was about delivering high-volume metrics that influence yields and cycle time.

For customers exploring new device architectures or preparing for High NA EUV critical layers, Intel Foundry offers advanced tools along with partnership in innovation, backed by proven integration expertise and a relentless focus on manufacturability.

 
Back
Top