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Search results

  1. F

    Chinese memory module makers ramp up production as CXMT DDR5 breakthrough hits market

    CXMT is working on 64-layer 3D DRAM, having already made 5 layers. https://ieeexplore.ieee.org/document/11399912
  2. F

    Chinese memory module makers ramp up production as CXMT DDR5 breakthrough hits market

    Founded in 2016, CXMT is widely regarded as China’s only domestic DRAM maker to have achieved mass production Howard Liuin Beijing Published: 7:30am, 14 May 2026 Chinese memory module manufacturers are accelerating the release of consumer and enterprise storage products powered by domestic...
  3. F

    Intel Prepares HBM Killer: HB3DM Memory Stacks with Z-Angle Technology

    At IMW, it was revealed these 8-high+logic die stacks are turned on their side and stacked laterally as tiles to form an inductively coupled network of tiles.
  4. F

    SK Hynix customers offering to buy EUV machines..

    It's almost like renting SK's space for the customers' own fabs 😆
  5. F

    SK Hynix customers offering to buy EUV machines..

    Don't know why it would be SK hynix and not Samsung, TSMC, Intel, etc. Possibly looking for discounts on the DRAM?
  6. F

    Intel delays 18A schedule: manufacturing problems slow down the hopeful centerpiece of the foundry offensive

    Is High-NA even necessary for 18A? It's not supposed to be, from some of Intel's own statements.
  7. F

    NEO Semiconductor's 3D X-DRAM for AI processors has passed proof-of-concept validation — company secures funding to develop next-gen HBM alternative

    4F2 comes in after 1d, but only lasts three generations. Since resources are being spent on 1d, 4F2, of course the 3D DRAM progress would be slowed down, but that only applies to the Samsung and SK hynix and maybe Micron. 3D DRAM is a long-term solution for the tier-1 guys but probably the big...
  8. F

    NEO Semiconductor's 3D X-DRAM for AI processors has passed proof-of-concept validation — company secures funding to develop next-gen HBM alternative

    This would be true for Samsung, SK hynix, etc. but it might be very different perspective for CXMT for example. CXMT is likely to skip 2D nodes going forward.
  9. F

    Qualcomm and CXMT jointly launch a standalone NPU + 3D DRAM, breaking through the performance bottleneck of mobile AI

    CXMT first discussed their 3D DRAM at IMW 2023: https://ieeexplore.ieee.org/document/10145931 Abstract: Continuous shrinking of dynamic random access memory ⟨DRAM) feature size will inevitably hit unsurmountable barriers, such as sub-10 nm patterning issues, ultra-high aspect ratio (HAR)...
  10. F

    SPIE 2026: Intel/Synopsys reveal ongoing EUV yield challenge

    Let's not forget a High-NA stitch is an extra pass.
  11. F

    Does DRAM refresh time represent a barrier to continued scaling?

    Yes, more Gb (expected in DDR5) also takes more clock cycles (tRFC) but those cycles could also be shorter.
  12. F

    SPIE 2026: Intel/Synopsys reveal ongoing EUV yield challenge

    From the abstract: Buried multilayer (ML) defects in EUV masks continue to pose a significant challenge to imaging fidelity and yield in 0.33 NA EUV lithography. However, it's only going to get worse with High-NA, which collects more light from smaller defects...
  13. F

    Does DRAM refresh time represent a barrier to continued scaling?

    The 3D DRAM in principle reduces the rowhammer risk with larger separations between word lines, but the JEDEC standard of 32 ms may be locked in at that time. The refresh rate is not that high a priority for scaling.
  14. F

    Does DRAM refresh time represent a barrier to continued scaling?

    The scaling will be most strongly impacted by distances within the DRAM cell itself. The VCT 4F2 architecture is motivated by the bit line approaching the capacitor active area contact too closely, while the 3D DRAM architecture comes from the capacitor itself becoming too thin.
  15. F

    Does DRAM refresh time represent a barrier to continued scaling?

    For DDR5/LPDDR5, refresh rate doubled from every 64 ms to every 32 ms. I'm pretty sure rowhammer had a lot to do with it. So this basically affects 1b onwards, although the issues started as early as 2x nm I'm sure.
  16. F

    Qualcomm and CXMT jointly launch a standalone NPU + 3D DRAM, breaking through the performance bottleneck of mobile AI

    Author: Su Ziyun | Publication Date: April 16, 2026, 12:13 PM According to Wccftech, Qualcomm is collaborating with Chinese memory manufacturers Changxin Memory and GigaDevice to develop a standalone neural processing unit (NPU) that incorporates 3D DRAM, attempting to overcome the current...
  17. F

    On Intel's Q1 Earnings: A Triple Test of CPU, 18A Yield Rates, and Foundry Orders

    Regarding new foundry customers: Timothy Arcuri: Thanks a lot. Lip Bu, I wanted to ask about the evolution of your foundry model. You are of course pursuing typical foundry customers, but it seems like TeraFab is a little bit of a different deal and maybe even like a process licensing...
  18. F

    On Intel's Q1 Earnings: A Triple Test of CPU, 18A Yield Rates, and Foundry Orders

    During the call, DZ said, "Intel Foundry operating loss in Q1 was $2.4 billion, improved $72 million quarter-over-quarter as better yields across Intel 4, Intel 3, and 18A drove higher gross margins. This was mostly offset by increased operating expenses associated with an intentional step-up...
  19. F

    On Intel's Q1 Earnings: A Triple Test of CPU, 18A Yield Rates, and Foundry Orders

    This article was written shortly before Intel's Q1 Earnings Call, but it still gives helpful perspectives on what Intel's future holds. Here are some excerpts: On April 8th, SemiAnalysis' chief analyst pointed out that CPUs are facing a very severe production shortage. Currently, the ratio of...
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