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Search results

  1. F

    Elon Musk throws shade on ASML's High-NA EUV machines

    Most likely Intel will be forced to follow same path as TSMC. It had no 14A customers at the beginning of the year: https://www.tomshardware.com/tech-industry/semiconductors/intel-says-it-has-two-prospective-customers-for-14a-expects-to-hear-about-commitments-in-second-half-of-2026. Terafab was...
  2. F

    Elon Musk throws shade on ASML's High-NA EUV machines

    Again, the clip does not provide the context of these comments. How this came up could be pretty interesting.
  3. F

    Elon Musk throws shade on ASML's High-NA EUV machines

    It could be the half-field size, or it could be directly exposing a smaller pitch (the resist).
  4. F

    The Truth Behind Huawei's 1.4nm LogicFolding Claim

    The red line trend is actually the plot of Density = 2 transistors/(gate pitch * cell height). They do state the 60-75% utilization factor, following the density formula. They are likely using 7nm node pitches, but can't rule out a reduction in cell height (i.e., less tracks). Die area...
  5. F

    The Truth Behind Huawei's 1.4nm LogicFolding Claim

    I developed this line of thought a little more here: https://www.linkedin.com/pulse/huaweis-logic-folding-cue-cfet-frederick-chen-xmnmc/
  6. F

    Elon Musk throws shade on ASML's High-NA EUV machines

    He did not specify in the clip why China will come out winning in the end (more power than anyone else, probably have more chips), maybe there were was something mentioned earlier.
  7. F

    Elon Musk throws shade on ASML's High-NA EUV machines

    "Half the chip for twice as much, for a gain that is relatively small."
  8. F

    The Truth Behind Huawei's 1.4nm LogicFolding Claim

    If Huawei defined the transistor density as 2/(gate pitch * cell height), and it's going from 155 to 238 MTr/mm2, it suggests that there is a big reduction in cell height. 155 MTr/mm2 is consistent with 57 nm gate pitch and six tracks of 38 nm pitch (228 nm cell height), while 238 MTr/mm2 is...
  9. F

    How does the HBF vs Xpoint technology

    It's recently proposed by SanDisk, in 2025. They are trying to get people on board, so far only SK hynix has engaged. So there are no standards yet.
  10. F

    How does the HBF vs Xpoint technology

    Yes, it's for inference. It won't displace HBM but complement it and ease the demand for it.
  11. F

    How does the HBF vs Xpoint technology

    I think a fair comparison would have the 3DXPoint dies linked by TSVs just like HBF and HBM (for 3D NAND and DRAM dies, respectively). The cost and performance were already not good enough for the 3D XPoint by itself to support a large enough market. The DRAM and NAND prices have gone up, but I...
  12. F

    LIVE: Intel CEO Lip-Bu Tan speaks at COMPUTEX

    Ok, by "untapped" capacity you mean room to improve. But the wafer cost is the same, so their margins need the yield.
  13. F

    Rapidus Completes 150 Billion Yen Funding Round from Japan Government

    If it's in R&D now, full-scale 2nm manufacturing by 2027 is definitely too soon.
  14. F

    Rapidus Completes 150 Billion Yen Funding Round from Japan Government

    Intel Fab 52 construction alone cost over 5 billion: https://www.enr.com/articles/62647-offsite-assembly-high-velocity-design-help-deliver-arizona-intel-fab-plant
  15. F

    TSMC CEO sends blunt message to memory chip rivals

    AI demand, particularly HBM demand, has gone up more than fab capacity can handle. Normally, higher prices would reduce demand from consumers, which in turn, would lead prices down. But consumers' demand no longer seems to matter compared to the hyperscalers, who are willing to pay more. Since...
  16. F

    Intel bit off more than it could chew with 18A process node

    CFO Zinsner insists the troubled node was a one-off as 14A stays on track Published Wed 03 Jun 2026 // 16:20 UTC Intel is keen to reassure investors that its troubles with the 18A manufacturing process were a one-off, and that it is better positioned to capitalize on what it expects will be...
  17. F

    Monolithic three-dimensional integration of silicon transistors

    Published: 27 May 2026 Monolithic three-dimensional integration of silicon transistors Monolithic, three-dimensional (3D) integrated circuits promise advantages in packing density, energy consumption and interconnectivity bandwidth but require forming high-performance semiconductors and...
  18. F

    Samsung GAA SF2, Exynos 2600, cross-section images

    This teardown by Kurnal was posted on X yesterday: https://x.com/i/status/2062125652288131276 Pitches are listed there, but the really interesting finding to me was that the number of M2P tracks in the cell height went from 6 to 5. Still 6 M0 pitches within the cell height though. No buried rails.
  19. F

    If Taiwan Falls, the Fabs Burn: Why TSMC's Destruction Is the Inevitable Outcome of a China Invasion

    Douglas C. Youvan doug@youvan.com www.youvan.ai January 16, 2026 The question of whether Taiwan Semiconductor Manufacturing Company (TSMC) would be destroyed in a Chinese invasion of Taiwan is often framed as speculative, controversial, or hypothetical. In reality, the accumulated logic of...
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