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  1. F

    Morgan Stanley reports Intel 18A yield at 50%

    Interesting comment from CFO here at Morgan Stanley conference back in March: https://ca.investing.com/news/transcripts/intel-at-morgan-stanley-conference-strategic-shifts-and-challenges-93CH-4495199 "As you might imagine, you know, when you’re, when you’re trying to like lock yields down and...
  2. F

    Morgan Stanley reports Intel 18A yield at 50%

    It was the same with the 7%/month. Probably safest to assume yield dominated by Panther Lake (~114 mm2).
  3. F

    Morgan Stanley reports Intel 18A yield at 50%

    Technology analyst Jukan pointed out on social media that, according to a report issued by Morgan Stanley, Intel's 18A process (compared to TSMC's 2nm) has a yield rate of only 50%, and the company is currently working hard to improve its yield level. The report indicates that customers have a...
  4. F

    Samsung SF2 transistor density benchmark against 18A and N3P

    Also brought up that's very interesting: 1. Intel 18A nanosheet vertical uniformity is better than SF2. 2. Samsung added a Heat Path Block (HPB), basically a heat sink above the CPU/GPU, sitting right next to the DRAM.
  5. F

    Samsung SF2 transistor density benchmark against 18A and N3P

    (coverage starts at 5:00)
  6. F

    Huawei plans 1.4-nm chips by 2031, Kirin 2026 Chip: 238 MTr/mm2 transistor density rivaling TSMC’s 3nm

    The metric 2/(CPP*Cell height) itself is not an issue since that information can be pulled for all the competitors; in fact, it might offer more clarity independent from layout utilization. The issue here is the formula should explicitly and unambiguously mention the use of stacking vertical...
  7. F

    Huawei plans 1.4-nm chips by 2031, Kirin 2026 Chip: 238 MTr/mm2 transistor density rivaling TSMC’s 3nm

    They shouldn't list the formula as 2/(CPP*Cell height) but maybe something like 2/(CPP*Cell height/# of vertical tiers), if that's their point.
  8. F

    Samsung GAA SF2, Exynos 2600, cross-section images

    So like CGP, we're seeing M2P leveling off around 28 nm?
  9. F

    Huawei plans 1.4-nm chips by 2031, Kirin 2026 Chip: 238 MTr/mm2 transistor density rivaling TSMC’s 3nm

    I see now, they plotted 2/(CPP*Cell Height). So this corresponds to ~114 MTr/mm2 if using the D_design formula, as expected for N+3. So then, to get to 238 from 155, LogicFolding is effectively reducing cell height and/or gate pitch? Arguably, making M2 the same pitch as M0 even by SAQP would...
  10. F

    China's Huawei reveals chip design breakthrough amid US sanctions

    Currently there is a report or rumor that Samsung is testing its 1.4nm on the next Exynos: https://wccftech.com/next-generation-exynos-tested-on-1-4nm-process-reveals-96mb-slc-cache-and-more/ but this soon suggests more likely not High-NA.
  11. F

    Huawei plans 1.4-nm chips by 2031, Kirin 2026 Chip: 238 MTr/mm2 transistor density rivaling TSMC’s 3nm

    I don't know if there has been a generally or widely accepted formula. I use 1.474/(CPP*cell height), it would be near the upper end of the D_design shown above. It comes from 60% NAND2 (3 CPP wide), 40% Flip flop (19 CPP wide).
  12. F

    Huawei plans 1.4-nm chips by 2031, Kirin 2026 Chip: 238 MTr/mm2 transistor density rivaling TSMC’s 3nm

    They have the ability to catch up, they just have to port their M2 to the same pitch as their M0. But with the speaker's emphasis on time instead of geometry scaling, it suggested they want to change the game.
  13. F

    Huawei plans 1.4-nm chips by 2031, Kirin 2026 Chip: 238 MTr/mm2 transistor density rivaling TSMC’s 3nm

    Just saw this: https://www.huaweicentral.com/huawei-kirin-2026-chip/ Huawei has revealed its Kirin 2026 details and it reveals massive upgrade in the chip architecture including transistor density. He Tingbo, Director and President of Semiconductor Business, revealed the Tao (τ) Law for chip...
  14. F

    Huawei plans 1.4-nm chips by 2031, Kirin 2026 Chip: 238 MTr/mm2 transistor density rivaling TSMC’s 3nm

    I wonder if this means they have stopped physical scaling.
  15. F

    Huawei plans 1.4-nm chips by 2031, Kirin 2026 Chip: 238 MTr/mm2 transistor density rivaling TSMC’s 3nm

    In a major bid to bypass crippling U.S. technology sanctions, China’s Huawei Technologies has unveiled an ambitious semiconductor roadmap, projecting the design of high-end chips with a transistor density equivalent to a 1.4-nanometer (1.4-nm) process node by 2031. The announcement was made on...
  16. F

    Corsair is now using Chinese DRAM in its DDR5 kits. Memory prices could finally drop.

    CXMT is also currently working on 64-layer 3D DRAM which should get them past the 0a-generation density.
  17. F

    Corsair is now using Chinese DRAM in its DDR5 kits. Memory prices could finally drop.

    May 23, 2026 - 9:37 am Story byAna Maria Constantin Corsair DDR5 modules spotted with Chinese CXMT chips as AI demand starves PCs of DRAM. Prices may fall in H2 2027 Corsair, one of the most recognisable names in PC components, is shipping DDR5 memory modules built with DRAM manufactured by...
  18. F

    Intel's Lip-Bu Tan: "B0 you keep your job, anything about that you are fired"

    Looks like extra pressure on Intel Product side, maybe to leave enough fab capacity for IFS?
  19. F

    World first: imec presents quantum dot qubit device using High NA EUV lithography

    From the scale bar, hard to believe it's 6 nm.
  20. F

    Intel CEO Lip-Bu Tan Calls Foundry a “National Treasure” as External Customers Knock on His Door After 18A Yield Turnaround

    I understand they've done speed bin splits before but never thought of those as "subpar".
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