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In response to the COVID-19 pandemic, EMA Design Automation is offering a work from home program in hopes to offset the challenges users may be facing while incorporating social-distancing into their daily lives. If engineers are asked to work from home, EMA will provide the resources needed so...
Most Oregon companies are asking workers to stay home and work remotely, public groups are limited to 10 people. Stores are still swamped with customers panic buying water, meat, bread, toilet paper, hand sanitizer.
Call for Papers
The 29th International Workshop on Logic & Synthesis - IWLS 2020
July 18 - 19, 2020, Moscone Center, San Francisco, CA
(co-located with IEEE/ACM Design Automation Conference)
Website: http://www.iwls.org
Paper abstract submission: April 17, 2020
Full paper submission: April 24...
At least in the fabs they are wearing bunny suits, which should provide adequate protection from the novel coronavirus, however once they change into street clothes and are in the locker room or lobby, then the virus can spread in those areas.
Kate Brown, Governor of Oregon announced tonight that all events with 250 or more people would be stopped for the next four weeks, in an effort to slow down the spread of coronavirus. Intel and Mentor are asking their employees to work remotely from home.
As a freelance blogger, I will continue...
DEADLINE: April 15, 2020
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DAC Ph.D. Forum
San Francisco, CA | July 19-23
The Ph.D. Forum at the Design Automation Conference is a poster session hosted by ACM SIGDA and IEEE CEDA for Ph.D. students to present and discuss their dissertation...
Barrie Gilbert of Beaverton died Jan. 30, 2020 at St. Vincent Hospital from a traumatic brain injury following a fall at home.
Barrie was born June 5, 1937, to Fredrick Arthur and Edith (Tansley) Gilbert in Bournemouth, Dorset, England. His father died in a bombing attack when Barrie was three...
Accellera Day opens the conference on Monday with a full morning tutorial, ““Portable Stimulus: What’s Coming in 1.1 and What it Means for You” presented by members of the Accellera Portable stimulus Working Group. An Accellera-sponsored luncheon will follow with updates on Accellera activities...
TSM is in 5th place as a MEMS foundry, behind: STMicroelectronics, Teledyne Dalsa, Sony, Silex Microsystems.
Lots more info at the Yole site. http://www.yole.fr/Top30_MEMS_Manufacturers.aspx
2020 Call for Papers
Original technical submissions on, but not limited to, the following topics are invited:
System-Level CAD
Synthesis, Verification, & Physical Design
SOC Analysis, Simulation, & Testing
CAD for Emerging Technologies, Paradigms, & Applications
Deadline for Abstract...
Munich, 03 February 2020 - PRO DESIGN, leading supplier of FPGA based prototyping systems, today launched its new proFPGA Cut software, a new design partitioning front-end tool for its popular proFPGA multi-FPGA prototyping platforms. This new tool significantly reduces the design bring-up time...
DATE 2020 is approaching fast and so is the deadline for the early-bird registration. Register online NOW in order to benefit from the early-bird registration fee.
Deadline: 5 February 2020, 23:59:59 CET
DATE 2020 will take place at Alpexpo in Grenoble, FR from 9 to 13 March 2020 and will be...
The 157nm immersion approach got us to sub-40nm lithography, however starting at sub-28nm we had to start using multi-patterning, or multiple masks per layer. EUV has a 13.5 nm wavelength and this allows the industry to do many of the critical layers in 11nm and smaller nodes. Mask costs are...
Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
12th International MOS-AK Workshop
(co-located with the IEDM and CMC Meetings)
Silicon Valley, December 11, 2019
Together with Silvaco, lead sponsor and local organization...
November 18-21, Denver Colorado
Booth #228, Aldec Inc.
We will showcase the recently introduced automatic FPGA partitioning feature of our popular HES-DVM™ tool, our fully automated and scalable hybrid verification environment for large SoC designs. Manual partitioning of designs with...
Munich, 18 November 2019 - PRO DESIGN, leading supplier of high-speed ASIC and SoC verification platforms, today announced the launch of its innovative high-capacity proFPGA quad Stratix® 10 GX 10M system. It is the next generation of its successful, modular, scalable and most compact...
The lawyers are going to get rich, and the two foundries will settle out of court, both claiming victory in the next 12 months or so. Such a common corporate tactic in high-tech to file countering complaints on patent violations.
I was also impressed with the 8.5 billion transistors of the A13 chip on the 7nm+ process, along with improved battery life. So glad to have invested in AAPL stock a few years back. Also amazed at the growth of services at Apple, but their streaming service is clearly not ready to compete with...
Tom, very comprehensive topics in your book with 700+ pages. I look forward to added content on topics like: packaging, 2.5D, 3D chips, chiplets, IBIS modeling.
