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It shouldn't make much difference, the pitch determines the resist thickness, which determines how many photons absorbed.
This is the latest study of 36 L/S nm pitch by Samsung: https://www.nature.com/articles/s41598-025-29021-2
I had gathered from TechInsights that the array area efficiency was just over 50% for 1b (LP)/DDR5, but also from them I only have one data point for HBM3 (1z), the array area efficiency was just under 50%.
The baseline defectivity is high even for a 40 nm pitch:
Since it fluctuates, you can have very good yield at times, very bad also. Stochastics hasn't been truly solved, accepted perhaps.
Not many HBM teardowns available but I had taken recent die area efficiency for the array ~50%, with TSVs ~10% (a strip down the middle). I might be over-generalizing though.
36 nm pitch has significant stochastic defectivity, which has been reported by Samsung and others (first by IMEC).
Samsung also confirmed the issue here as well...
The author likely only had info from her domestic sources. But the story is incomplete without Micron and how much it could produce. Presumably a similar story.
The large swings of yield can come from the intrinsic variation of stochastic defect density, but other systematic factors related to process control can also be contributing, perhaps comparably.
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I thought mainstream OTP is precisely breaking down a transistor's gate oxide!
It can be made using advanced node CMOS.
A 28nm 2T cell ~ 0.05 um2: https://ieeexplore.ieee.org/document/10183939
