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Search results

  1. F

    Panther Lake design rules revealed, no HD cells

    We've heard that 18A yields were still on improvement path toward the end of 2025. Parametric yields could also result from stochastics as manifested in uniformity. But EUV yield is intrinsically erratic, since the D0 (from stochastics) can vary over an order of magnitude.
  2. F

    Panther Lake design rules revealed, no HD cells

    If Backside or GAA/RibbonFET are new sources of yield loss, then relaxing to 36 nm pitch looks understandable. That said, high defect density at 36 nm pitch has been noted publicly before by imec, Samsung, and even (indirectly) TSMC.
  3. F

    Panther Lake design rules revealed, no HD cells

    Some key Panther Lake design rules were posted on X: Minimum pitch 36 nm (7nm-class), density obviously helped by 5 tracks from backside rails.
  4. F

    Did Intel just delay their 14A node by a year?

    Did Intel just delay their 14A node by a year? At Cisco's AI Summit this month, Intel CEO Lip-Bu Tan announced that Intel's 14A node will be in risk production in 2028 and volume production in 2029, representing a 1 year slip from prior disclosures of a 2027 risk production start date. The...
  5. F

    SMIC BEOL photolithography process analysis / N+3 yield issues

    Yes, a 32 nm pitch direct EUV print is highly risky and ppm-level defect probabilities have already been reported in several published sources (besides myself, Samsung/ASML and imec/Siemens) for 40 nm pitch and below. Probably even more difficult is the wide range (over an order of magnitude) of...
  6. F

    SMIC BEOL photolithography process analysis / N+3 yield issues

    Ok, I'm not sure if the author is doing solely a speculative analysis or has the teardown. Author mentions five M0 tracks, but the cell height is determined by six 38 nm pitch M2 tracks (=228 nm). I had the understanding that TechInsights did the analysis for this, so I'm not sure if that is...
  7. F

    SMIC BEOL photolithography process analysis / N+3 yield issues

    It looks similar to what I had analyzed and written before: https://chentfred.substack.com/p/kirin-9030-hints-at-smics-possible...
  8. F

    Softbank Corp, Intel announce memory chips collaboration

    Seems early, but probably so, if the companies allow.
  9. F

    Softbank Corp, Intel announce memory chips collaboration

    A zoom-in on the slide confirms this picture as well: https://www.techpowerup.com/345929/intel-and-softbank-subsidiary-saimemory-partner-on-next-gen-z-angle-memory#g345929-2
  10. F

    Softbank Corp, Intel announce memory chips collaboration

    This picture is more accurate than all those ridiculous AI-generated art with diagonals. The idea is to have more DRAM dies stacked laterally on their sides. The interconnects between the dies are part of the package rather than going through the dies. The referred Intel patent application is...
  11. F

    CXMT Plans to Allocate a “Large Chunk” of Its DRAM Production to HBM3, Hoping to Compete in the AI Race

    Feb 10, 2026 at 11:18am EST China's CXMT is expanding its presence in the HBM market, aiming to capitalize on the AI frenzy, as the company is now reported to be converting a large chunk of its DRAM output. CXMT's Capacity Shift Towards HBM Does Put the Idea of "Cheaper" Consumer Memory Under...
  12. F

    Leading PC manufacturers considering using Chinese memory chips, report claims — HP and Dell qualifying CXMT DRAM

    PC makers are getting desperate for memory chips. The ongoing memory chip shortage is forcing leading PC makers to consider sources outside of the traditional big three suppliers — Micron, Samsung, and SK hynix. According to Nikkei, sources say that Dell and HP have started qualifying DRAM from...
  13. F

    Softbank Corp, Intel announce memory chips collaboration

    I don't think any benefits have been confirmed, not even a publication with simulations.
  14. F

    Softbank Corp, Intel announce memory chips collaboration

    Intel did not release any schematics, and there are plenty of AI-generated pictures around :ROFLMAO: But from this graphic, it looks like combining vertically stacked DRAM dies and EMIB.
  15. F

    Changxin Storage's low-price sell-off of DDR4 reported incorrectly

    Perhaps the best argument is, could CXMT already have enough DRAM supply, even with expected low yield, to disrupt the market as claimed?
  16. F

    Changxin Storage's low-price sell-off of DDR4 reported incorrectly

    2026/02/04 13:11:08 Economic Daily reporter Cui Xinfang/instant report In response to recent media reports pointing out that Changxin Storage (CXMT) sells DDR4 at a much lower price than the market price, raising market doubts about the price trend of the old generation memory, and the market...
  17. F

    Bottlenecks in DRAM and HBM: Tailwind for China's Memory Industry

    Almost certainly, all of it is going to domestic customers, and it's likely not enough to go around even there. But in the outside chance it does go to US, we'll have to see what mood Trump is in.
  18. F

    Bottlenecks in DRAM and HBM: Tailwind for China's Memory Industry

    2026-01-21 Henrik Bork For the construction of AI data centers, so many DRAM memory chips are needed worldwide that there are no longer enough left for manufacturers of smartphones and computers. The current situation gives Chinese manufacturers like CXMT a boost. The demand for memory chips...
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