Semiwiki on LinkedIn Semiwiki on Facebook Semiwiki on Twitter Register / Log in 
Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/search/327729/?c%5Busers%5D=Fred+Chen&o=date&page=2
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2030770
            [XFI] => 1060170
        )

    [wordpress] => /var/www/html
)

Search results

Search the forum Search Semiwiki WordPress
  1. F

    Solidigm: NAND industry facing fab shortfall

    By Chris Mellor November 21, 2025 The NAND industry is facing a 3-year NAND chip output shortage as new fabs will take years to build. This was the message from Solidigm at an A3 Tech Live session in London. The company is a 100 percent owned subsidiary of SK hynix who bought it from Intel...
  2. F

    SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC Is to 5nm

    So far, all that TechInsights has released without subscription is that it had "aggressively scaled metal pitch using DUV multi-patterning." So it's possible.
  3. F

    Intel Installs ASML TWINSCAN EXE:5200B High-NA EUV System for 14A Process Node

    Their own High-NA update a few days ago makes no mention of any node, let alone 14A. https://community.intel.com/t5/Blogs/Intel-Foundry/Systems-Foundry-for-the-AI-Era/How-Collaboration-in-High-NA-EUV-and-Transistor-R-D-Are-Shaping/post/1730050
  4. F

    Cleaning damage to EUV masks (NYCU/TSMC SPIE BACUS 2025 paper)

    The new capping layer also oxidizes after cleans, so that's possible.
  5. F

    Cleaning damage to EUV masks (NYCU/TSMC SPIE BACUS 2025 paper)

    Cheaper/faster to re-pell; clean the mask at that time.
  6. F

    PAX SILICA

    The launch of Pax Silica ended the fragile trade truce established between President Trump and President Xi Jinping in November 2025. Chinese officials see the initiative as a fundamental threat to their industrial goals and a violation of that agreement’s spirit. In response, China’s Ministry...
  7. F

    PAX SILICA

    Taiwan’s status was one of the most closely watched aspects of the summit. As home to TSMC and a central player in the semiconductor industry, Taiwan was designated a “guest contributor” rather than a founding member. State Department officials highlighted Taiwan’s importance as a trading...
  8. F

    Cleaning damage to EUV masks (NYCU/TSMC SPIE BACUS 2025 paper)

    This should also apply to the EUV resist.
  9. F

    Cleaning damage to EUV masks (NYCU/TSMC SPIE BACUS 2025 paper)

    Repeated cleans were found to cause peeling of the Ru capping layer and multilayer damage, due to oxidation of the Si/Mo layer underneath.
  10. F

    Cleaning damage to EUV masks (NYCU/TSMC SPIE BACUS 2025 paper)

    EUV lithography patterned intricate layers with small feature on a wafer using a reflective EUV mask. However, the EUV lithographic environment, often containing water vapor and hydrocarbons, introduces molecular contamination from secondary EUV electrons, degrading reflectance stability ...
  11. F

    SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC Is to 5nm

    It was said to be ~40% better than 9020, but lagging behind the Qualcomm, Apple flagships.
  12. F

    SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC Is to 5nm

    Actually TSMC N7 to N5 M2 pitch shrink (40 nm to 35 nm) wasn't enough by itself to justify a node change. Gate pitch shrink was also significant for transistor density. You might say, SMIC lagged in gate pitch too much from N+2. Yet, the patterning for gate pitch won't change, so that is not the...
  13. F

    SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC Is to 5nm

    TSMC N6 changed diffusion break from double to single, that in itself is enough to put it above 100 MTr/mm2. So it is a noticeable jump in density from earlier 7nm. The design rules were (supposedly) the same as N7 though I think gate pitch shrunk to 54 nm to get the number below. I had...
  14. F

    PAX SILICA

    Probably fear of China
  15. F

    SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC Is to 5nm

    I'd picture it this way...
  16. F

    SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC Is to 5nm

    This article explained that some discrepancies may arise, depending on the layout assumptions, such as the ratio of NAND to Flip-Flop: https://www.angstronomics.com/p/the-truth-of-tsmc-5nm I used the formula in that article, but actually I applied it wrongly for the 7nm generation nodes since...
  17. F

    SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC Is to 5nm

    Yeah, I remembered the gate pitch had been "abnormally" large, but actually it's just that SMIC density < Samsung density < TSMC density for a given process family or cluster.
  18. F

    SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC Is to 5nm

    I went back to check the numbers, what I have is: I am not sure if SMIC N+2 density was ever released or calculated?
  19. F

    SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC Is to 5nm

    I'm just going after the "significantly less scaled" than Samsung "5nm" part.
  20. F

    SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC Is to 5nm

    My objection to TechInsights' or Jukan's spin is that the difference between TSMC's and Samsung's 5nm densities is more than the difference (or ratio) between Samsung and SMIC.
Back
Top