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It depends on the process flow, exposure tools run >250 wph, CMP 60 to 80 wph, implant can be up to 500 wph for some tools, etch varies a lot, for example 3D NAND channel etches can be an hour per wafer. I plotted throughput by tool type for a whole variety of processes once and the data points...
By the way, I say horizontal nano sheets (HNS) because GAA is a more generic term, in fact VFETs if ever used will likely be GAA as well. I don’t think we will see VFETs because they don’t have the long incremental scaling path that HNS do.
CFET is an evolution of horizontal nano sheets so most likely we will see horizontal nano sheets (Samsung multi bridge, Intel Ribbon FET) for a few nodes and then later this decade CFET. Going out into the 2030s stacked 2D layers will likely come in. The semiconductor industry is very risk...
You are mixing up and trying to compare two completely different ways of measuring density.
If you want to compare processes to each other you can't base it on designs because designer decisions can dramatically change density even on the same process. I have written about the problem here...
Are you asking for transistor count or transistor density? You ask for count but your description sounds like you want transistor density.
I have published density comparisons here: https://semiwiki.com/semiconductor-services/ic-knowledge/310900-can-intel-catch-tsmc-in-2025/
Planar FDSOI can only scale a few nodes, even FDSOI pioneer CEA/LETI had their scaling roadmap being FDSOI and then GAA takes over.
FinFETs are higher performance for leading edge applications and have scaled a lot faster than FDSOI.
You can make a FinFET on SOI, in fact IBM 14nm was FinFET on...
The 10% performance is a little less of an advantage for TSMC than I would have expected, the 30% better power is actually less too. Samsung 3nm with Horizontal Nanosheets is supposed to close a lot of the power gap versus TSMC but the yields are awful.
I am laughing right now, this chart made my day. Divide the wafer price by 2 and you will be close, the mask set cost is off by even more. There is a limit to how much wafer prices can go up with each new node if you want to sell them, $50k is way outside of that range and way outside of the...
I expected TSMC to follow 2nm with something like 1.5nm so 1.4nm doesn’t surprise me. What will be really interesting is how it is made. 2nm is pretty much known to be horizontal nanosheets (HNS),1.4nm could be a second generation HNS or we could see a CFET.
There are reports out of Asia that TSMC 3nm development team is switching to 1.4nm and speculation about what that means. The speculation suggests 1.4nm is next after 3nm or replaces 3nm or.....
Here is my take:
3nm is due to enter production shortly, therefore development is done.
2nm...
It is all production and development 300mm fabs making semiconductor wafers, it does not include 300mm fabs focused on packaging such as the TSMC fabs running InFO.
Generally speaking this is the electrical yield at wafer sort and it is the percentage of die that meet a set of electrical specs. If you get defect density from a foundry it will typically be extracted from a test chip once again to the process specs. Yes if you relax the specs the yield will...
We will see, it is possible they were exploring the possibility but haven't decided. Once again. TSMC hasn't announced it and construction hasn't started so it is a couple of years away if it actually happens. TSMC has explored other fab site/options that they didn't do so until TSMC says they...
But TSMC has made no announcement on a Kaohsiung fab and until they do I question how real this is. I also don't think the 7nm and 28nm in the same fab comment makes sense.
My mistake on Nanjing, they did say they are expanding 28nm capacity on their 2021-Q4 earning call and they did mention China as one place they are expanding it. In term of Nanjing on the 2021-Q2 call they said the total capacity is 25k wpm in phase 1 and phase 2 will come on line second half...
