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When comparing wafer costs there are two components, one is process cost and the other is fab cost. Intel 10/7 processes are very expensive processes compared to TSMC 7nm even if run in the same fab. Intel fabs are generally in higher cost countries plus Intel has some Intel specific cost...
This is an interesting slide:
- Performance/watt - I agree with their ratings.
- Density - I don't agree with, TSMC is way ahead of 18A, maybe Intel could catch up at 14A but it would take a huge jump.
- Wafer cost - surprisingly, I was just looking at wafer cost and through 18A I think they are...
"The cost of 2nm chips is very high. Research institutions pointed out that compared with 3nm, the cost will increase by 50%, and the single cost of each wafer will climb to US$30,000; therefore, the first batch of adopters will still be smartphone chips. Customer—Apple."
When 3nm was still in...
"As many on this forum are aware, maximum theoretical logic density is often calculated by taking the (M2 pitch) X (M2 tracks for a four transistor NAND gate) X (CPP). From there we try to use correction factors to account any boundary scaling (for example Scotten using 10% area reduction from...
The connection is from the side just like for the Power Via.
"As a side note why do you think that AMAT and intel have a different definition of what BPR is from IMEC? The engineers from both firms are far from dummies, and they both contribute to IMEC. The difference in opinion and definition...
My understanding is the process is:
1) Transistor formation and front side interconnect formation on the front of the device wafer.
2) A carrier wafer is bonded to the front of the device wafer.
3) The wafer pair is flipped over and most of the device wafer is removed from the back.
4) Through...
We are running 3nm now with 2nm (20A) due 2024 to 2026 depending on version and company. Samsung has talked about 1.4nm in 2027 based on a Horizontal Nanosheet with more sheets. My projections are 10A around 2029 based on a CFET, with 7A, 5A, and 3A CFETs to follow. Finally around 2037 we get...
Aluminum for what, are you talking Buried Power Rail (BPR) because Al won't survive the temperatures or meet the electromigration requirements. If you are talking Backside Power Delivery that is copper and it is done at the end of the process flow.
It not quite 2x density due to interconnect requirements but it is a big jump. 2D gives a big jump in CPP and therefore cell width, and CFET gives a big jump in cell height by doubling up the transistors and eliminating the horizontal n-p spacing.
My estimate is 1,500 MTx/mm2 in 2037.
Do you have a reference for that demonstrator, I have never heard of that and never heard/seen anyone talk about it and I am very plugged in to that community.
As is CFET and both Intel and TSMC have published on it extensively and both have shown slides with CFET as a post HNS option. Neither has talked about VTFET.
My own, I have been analyzing this path for many years, I have a presentation of over 60 slides that walks through the whole path and has been shared with/reviewed by a select group of experts.
It is nanosheets rotated 90 degrees.
I don't see this as stackable and it isn't a CFET.
It looks to me like the vertical nanosheet would be lithographically defined and that has more variability than the epitaxially defined horizontal nanosheets (HNS).
As I noted above I don't see this as...
Once you make the change from FinFETs to Horizontal Nanosheets (HNS) you open up a scaling path that will carry us for over ten more years of logic scaling. First there will be multiple generations of HNS, then multiple generations of CFET, and eventually 2D material CFETs. We are currently at...
"VTFET main allure is the "free" path to monolithic 3D, which horizontal devices don't have."
How did you come to the conclusion that this is a stackable technology? It's not clear to me that this is stackable and that isn't what the paper discusses as the advantage of this technology.
