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Some technical details about BPD and some of the process challenges of getting it to work:
https://semiengineering.com/challenges-in-backside-power-delivery/
Some clues below as to why BPD is only being introduced at 2nm -- basically, lots of process and materials and flow changes are needed...
I've been trying to answer your question about adding BSPDN to 12nm, and specifically the issues with process and IP that would result from doing this, based on >30 years of experience talking to foundries about doing such changes -- I've been there many times before with "wouldn't it be nice if...
IIRC the issue isn't really durability, it's SEU. But no way are SpaceX going to spend a fortune -- and greatly increase TTM -- having customised chips developed for all the electronics in their satellites, they'll take existing stuff they can get hold of and radiation test it. DAMHIK... ;-)
This is why actual cell utilisation compared to theory is lower than it used to be and is still dropping each node. BSPDN is a way to try and recover this, as well as improve PDN integruty.
You clearly don't have any idea about the consequences of making a change to a process, especially such a major one as adding BSPDN -- which anyone who understands processing will be aware is a huge challenge for all sorts of reasons, otherwise foundries would have done it years ago. They're...
Those are "nice-to-haves" -- real benefits mean cheaper, or lower power, or faster, or reduced TTM.
Will it be cheaper than standard 12nm/16nm? No, probably more expensive -- die might be a bit smaller but wafer cost increase is likely to outweigh this. Does it gain a bit of power/speed...
What is the benefit to the fab? What is the benefit to the customer?
I'd love to try and see you automatically port an 80+GHz PLL/clock distribution with multiple coupled inductors, since this is difficult enough to do for the designers who know how it works and what everything does... ;-)...
You're still missing the point -- it's not the equipment cost as such, it's the foundry having the incentive to do all this for a relatively small gain, because 12nm and up doesn't have anything like the power/metal/routing problem that 2nm does.
Changing a process -- not just equipment/flow...
OK, let's say TSMC decide to "give their 22-14nm" some love and implement BSPDN. Every single library cell (digital, RAMs, analog) has to be completely redone for layout and re-extracted and simulated -- which also means all the IP in the TSMC ecosystem. Then the process itself has to be...
Nothing's ever *absolutely* essential (except EUV for 3nm and below...), but the advantages of BSPDN become pretty strong at 2nm and more so beyond that -- it's not that you can't do 2nm without it, but it's worth the effort even given the cost and difficulty since the wafers will cost a fortune...
I can't give any numbers (team size/design cost) for obvious reasons, so I was kind of hinting that this isn't something you can do with a handful of engineers and a small budget, unless it's a simple low-speed transceiver ;-)
To give you an idea, IIRC the license fee in $ for a leading-edge...
That's like asking how long a piece of string is. The effort depends very heavily on the type of transciever and the channel it has to drive, for example a long-reach 112G PAM4 transceiver is *way* more complex and needs *far* more design effort than a short-reach 16G one.
The bigger geometry processes don't have such big routing/metal density/voltage drop problems as 2nm and below. Adding backside power (and the TSVs and wafer bonding/thinning and...) is not easy or cheap and needs a lot of process change/infrastructure/qualification, no foundry is going to do it...
They're for optical fiber networks in the internet backbone, reach can be anywhere between 10km to 10000km depending on application.
Jitter is measured with a phase noise/jitter analyser, these can easily measure down to 5fs.
Don't know what the ratio between analog/RF and digital is, design...
The one in the photo -- there are >100k of them out there now -- is a 400G coherent transceiver -- and you're right, jitter is of the order of 100fs. PLL inductor is on-chip, frequency is too high for off-chip.
Most of the NRE is the design/development cost of the chips not prototyping the MCM...
This is one reason why backside power is pretty much essential at 2nm and below, the fine-pitch metal for signals is then above the FETs and the high-current coarse-pitch metal for power is below them. This avoids the need to get the power down past the thin high-resistance signal routing...
