You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
Following the rules -- including voltage-dependent spacings, and gate pitches -- should ensure a reliable and high-yielding design, that's the entire point of them. But this assumes that the foundry has spotted all the possible "gotchas" in the layout, which often involves trying out a huge...
I'm sure we'll never get any public admission of *exactly* what went wrong, it would be too embarrassing for Intel and possibly helpful to IFS competitors -- the most we're likely to get is the current admission of "too hard"... ;-)
There were rumours about various problems with the process...
Who are famously good at coming up with really sexy advanced technology that turns out to be difficult to manufacture/yield (see also Samsung...).
The perfect fit for Intel, then... ;-)
Having the performance (or density) isn't enough, that's not what lead to Intel's 10nm debacle -- it was yield and reliability problems getting the process into production, either because of too small a process window (pushing the rules too hard -- even TSMC have hit this (e.g. in N3, hence only...
22FDX is also good for analog/mixed-signal (back-gate tuning, device stacking, multiple device types up to 6.5V DMOS, high Ft for both NMOS and PMOS) which is why many customers use it -- along with good (but not state-of-the-art) digital. I think 12FDX offers little or no advantage over 22FDX...
12FDX has been on the cards for many years but has never made it into production, presumably because the added double-patterning complexity over 22FDX increases cost considerably but without much improvement in PPA -- customers wanting high-density digital will go to FinFET at 7nm and below...
I'm not 100% sure how FinFlex mixing works, but I believe that you define the FinFlex configuration (1-1,1-2, 2-2, 2-3) for an HLB (High Level Block) depending on speed/power/density requirements -- mixed sizes are always alternating large/small rows -- and the tools then optimise (Vth and...
It's not just speed-sensitive blocks but also individual gates, when doing timing closure without FinFlex the tools will choose different transistor types to trade off speed/dynamic power vs. leakage (e.g. ULVT, LVT, SVT -- which can be mixed), FinFlex just adds another set of gate options to...
There's also the issue with N2/N2+ that this transition is *not* like previous half-nodes (e.g. N7/N6, N5/N4, N3E/N3P) where all the IP is reusable -- the PPA attraction of N2+ is BPD, but this needs a complete relayout and recharacterisation of all IP, new libraries (standard cell/RAM) and...
Actually N3P (a tweaked 2% linear shrink of N3E) is looking more likely to be "the big one" -- I heard from our digital team that TSMC has upset a lot of people by accelerating the N3P schedule and short-cutting N3E, as a consequence everyone is moving to N3P while complaining that the libraries...
What is actually different about this compared to GAA/nanosheets? Is it nanosheets but rotated 90 degrees so they're on edge not flat? Or is it just another name for CFET? (NMOS and PMOS stacked vertically)
That's not what I said. They won't drop FSPD, they'll bring forward BSPD and offer both, FSPD for customers who prioritise lower risk/higher yield and BSPD for those who prioritise PPD. It's what they've done for years with process variants and "half-node" steps. It's quite possible they...
I see a clear dividing line between N2/FSPD and N2P/BSPD -- in terms of design/layout/tools N2 is the last member of the FSPD family (including N3) with GAA dropped in instead of FinFETs (like 16nm), N2P/BSPD is the first member of the next-generation processes -- for customers the...
I suspect most TSMC N2 customers will wait for the 2nd generation N2 process with backside power (like Intel 18A), which will also have much more in common with the nodes that will follow.
Apart from having better performance for both signals and power (and higher density), the layout of IP...
It all depends how TSMC N2 compares to N3. From what I've seen I believe it's basically a similar metal stack (slightly reduced pitches) but with new transistors dropped in underneath -- GAA instead of FinFET, like TSMC 16nm dropped in FinFETs instead of planar MOS in 20nm -- then it won't be...
