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I don't think there's much doubt that BSPD will deliver the *technical* benefits claimed -- lower voltage drops and access resistance, easier signal routing due to lack of conflict with power routing.
Whether there will be corresponding technical *disadvantages* -- worse hotspots, cooling...
Given that thermocouples/thermoelectric coolers are very inefficient and power-hungry, using them to try and cool "hot chips" will increase overall power dissipation, not reduce it... :-(
I don't think we're disagreeing here... ;-)
One problem is that "PPA" is too simplistic -- if one process is better on all three counts (power *and* performance *and* area) than another then it's obviously "the best", but that's not the issue here -- it's not even the case with the different...
The argument about who is right about whether 18A or N3P is better misses the point, which is that there's not always a single "better", depending on the process priorities.
Historically Intel have valued performance (clock rate) over everything else (density, power consumption, yield...)...
That's true up to a point, but it can rarely completely fix yield problems though it can certainly improve yield from extremely low to acceptable -- if it was a complete fix then there would be more full-reticle chips and they'd be cheaper... ;-)
Plenty of reticle sized chips at TSMC and elsewhere, but even with TSMC defect densities -- which AFAIK are the best in the business -- the yield of such monsters is always going to be low. But then if the chip ASP is a high four-digit or even five-digit number, even percentage yields of 10% or...
The difference is that ASML are in the area where equipment costs are going up the fastest (EUV and soon low-NA EUV) because it's fundamentally new technology that they have an effective monopoly on, other equipment costs like those for Applied Materials are not rising so rapidly -- which means...
Don't see where "talking down the competition" comes from -- we have no intention of using Intel until their level of support for foundry customers and IP availability is comparable with TSMC, which I suspect will never happen, so there's no incentive for TSMC to talk down BSP. In fact the...
Also:
https://semiwiki.com/semiconductor-manufacturers/342094-iss-2024-logic-2034-technology-economics-and-sustainability/
"Logic transistor costs go up at 2nm the first TSMC HNS sheet node where the shrink is modest. We expect the shrink at 14A to be larger as a second-generation HNS node...
I was simply relaying what TSMC told us when we asked which process we should be targeting after N3... :)
At the IP level BPD is more disruptive to layout -- especially things like high-speed SERDES -- than going to GAA, which just swaps in a different transistor at the bulk level. With BPD the...
You need to be careful about making assumptions like "backside power is best" -- TSMCs recommendations for N2 is that the BPD process is targeted at applications like CPUs where flat-out speed at elevated voltages (high current density) matter more than cost (BPD process will be more expensive)...
Because they're the worst cases for speed (X) and power (Y) -- X axis is slowest (slow transistors, low voltage and temperature), Y axis is highest power (fast transistors, high voltage and temperature).
I think this is showing how little the improvement from raw process is nowadays, which is not that surprising when you look at how small the layout differences/pitches are between N5/N4 and N3. There's quite a big density (area) improvement (not so much from just pitches, also from DTCO) and the...
I guess like anything else the first one takes a lot more time and effort, which then decreases as more and more are rolled out.
Still expensive, massive, hot and heavy though... ;-)
The hybrid libraries in N3 make things really interesting, from the benchmarks we've seen they decrease power and area but don't increase speed for obvious reasons (H169 is 2 fin, M143 is mixed 1-fin/2-fin).
