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Yes. Most of the PPA improvement we saw from N5/N4 to N3 were due to the mixed-height FlexFin libraries -- the high-density M143 library is actually alternating rows of 1-fin H117 (for low-power non-critical paths) and 2-fin H169 (for critical paths), and there are also tall H286 cells (one row...
I doubt that anyone will disclose exact pitches and changes to cell structure/layout with N2 because of NDA, but there are various detail changes -- some not obvious -- to increase density and improve access resistance both with N2 and N2-SPR. The metal stack is similar to N3, no big changes...
Same for Intel, the reasons are the same even though the exact implementation is different -- but of course all Intel's products are high-speed high-current, unlike TSMC (who also have N2P for the others). Maybe Intel took more risk (more radical BSP structure) and TSMC decided to play it safer...
For example, the "TSMC headline figures" for A16(SPR) vs N2P are +8%-10% speed, -15%-20% power, +10%-15% logic density, +5%-8% chip density.
But this is for high-current fast-clocking chips with a high PWR/GND grid density (20%-30%), which is what they benchmark with -- a lot of the savings...
That's because there's very little change in the metal pitches from N3 to N2 or A16 (renamed N2 with BSPD).
N3==>N2 is similar to 20nm==>16FF (different transistors, similar metal stack), N2==>A16 is just going from front-side to back-side power.
In both cases there's a significant...
Do note the small print for A16-SPR though -- the power/speed/area improvements are for "Datacenter AI products", or from the slide "Best suited for HPC products with complex signal routes and dense power delivery networks".
In other words, big chips with relatively high clock rates/supply...
I meant lower-than-ELK dielectrics in the metal stack, since wiring is now where a lot of the capacitive load (and therefore power consumption) is.
For high-speed circuits which are on all the time you use fast but leaky ELVT transistors, but many applications have blocks which are not always...
That's what I meant when I said lower C isn't going to save us, it's not dropping very rapidly -- even lower-K dielectrics are unlikely, wires are getting more densely packed, gate capacitance is dropping a bit as smaller transistors give more drive but again this is low -- real channel length...
Even if the problem of thermal resistance though the stacked chips can be magically solved, that still leaves the power density problem, which is still going up none-by-node because density is growing faster than power per gate is decreasing, and there's no signs of this getting any better -- in...
If you look at the power/performance curves from one node to the next, for power-critical applications you find that somewhere not far off the same performance (clock rate) is the best choice -- you drop the voltage a bit (maybe a few 10s of mV), keep the same clock rate, and save power/flop...
The problem with stacking for logic (unlike memory) is power density and heat extraction; the power density (W/mm2) for a single layer of logic is already going up node by node because density is going up faster than power per gate is shrinking, so it's getting more and more difficult to cool...
I said that gaming PCs (CPUs) are a relatively small and shrinking part of the total leading-edge silicon market; yes they're still growing -- at least, for the time being -- but the total market is predicted to grow faster, and the vast majority of this growth is predicted to be in AI...
All true -- but you're still looking at today's HPC, which is not where the massive use of these processes is predicted to be... ;-)
Nvidia standalone GPUs are trying to push the biggest performance possible out of a given-sized piece of silicon, often reticle sized in their biggest parts --...
Regardless of what gamers think, gaming PCs (CPUs) are a relatively small and shrinking part of the total leading-edge silicon market -- the dominant market driver in these timescales (18A vs. N2) will be HPC at the hyperscalars, more specifically AI which will be >10x bigger than gaming CPUs --...
Except "perfomance" in HPC nowadays (and especially in future) is more likely to mean "most efficient/dense" not "highest clock rate", especially in what is predicted to be the dominant market driver which is AI not traditional CPUs.
The problem Intel may have is that they still seem to mentally think "HPC=Highest GHz clock rate" because this is the marketing point for their x86 CPUs -- fastest single-core boost frequency to make a headline against AMD, for example.
This is less and less important even for desktop/laptop...
Yes, but even the TSMC HPC libraries are denser than Intel -- as Scotten said above Intel use more relaxed design rules and fewer EUV layers (and presumably fewer DP EUV layers too...) so 18A is just plain inherently less dense.
OTOH it may have higher ultimate performance, if you can afford...
When you say
I assume you mean it's lower cost *per wafer* (in the same fab)?
Given the density difference (IIRC this is quite large?) this could mean the cost per chip (same function) is similar or maybe higher in 18A than TSMC 2nm -- and that's ignoring yield and fab utilization (and running...
