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Maybe that's because the server market is not very price-sensitive but the laptop market is, Intel Foundry wafer/chip costs are higher than TSMC, so they use TSMC where cost matters and Intel where it doesn't?
It certainly does, going by the numbers we've seen... :-(
As for A16 with BSPD, the Rolls-Royce principle applies -- if you have to ask how much it costs, you can't afford it... ;-)
BSPD helps with power delivery, means clock rates can be increased, density goes up a bit all of which increases power density in W/mm2.
But we're finding self-heating is becoming an increasing problem, especially for high-speed circuits such as SERDES. BSPD increases thermal resistance in the...
I'm not in any way doing down what TSMC have done with N3 (and now N2), their strategy has been excellent -- the problem is they're coming up against fundamental physical limits like gate length and the problems of getting low-resistance access to tinier and tinier transistors crammed together...
The critical parameter that's really slowed down per node though is power consumption -- density is still increasing, power has almost stalled, which also means that power density (self-heating) is going up. This is increasingly a problem, especially for high-speed circuits, and backside power...
I was going by actual synthesized digital layouts (standard cell logic) that we did as opposed to simply looking at the design rules -- and we saw very little improvement in power for N3 compared to N5 using comparable libraries (2-fin), the improvement going to FINflex was considerably bigger...
None of this should be any surprise because CPP and MP scaling has pretty much stopped -- N2 is pretty much N3 with HNS replacing FinFETs, and A16 is precisely N2 with backside power.
Actually this applies to N5 too, CPP and MP are similar to N3 -- going by our benchmarks the main reason for...
Even with N7+ TSMC only used the minimum number of EUV masks -- and they also learned a valuable lesson because N7 and N7+ layouts were incompatible so new IP and libraries were needed, so very few customers used N7+. Good for TSMC because they could debug EUV on a relatively low-profile process...
And N2 is pretty much N3 with HNS transistors replacing FinFETs, the basic pitches (metal and contacted poly) hardly changed. That's three headline process generations (N3/N2/A16) with almost identical underlying technology...
If you want another example of how marketing has taken over the...
I believe the figures I saw for area/speed/power changes vs. power grid density (which I can't disclose) came from actual TSMC like-for-like layouts (same basic libraries) not theoretical calculations, so I'm inclined to believe them.
The quoted wafer cost increase we were given for A16 over...
There's no doubt that TSMC will get customers for A16, including some big ones, for who it has significant advantages. I'm just trying to calm down the over-enthusiastic reception in some quarters who think it's a sexy new technology which is going to take over the silicon world and make things...
The points missing from all Intel's presentation about PowerVia (and most of TSMCs) is that the performance/area improvement depends heavily on power grid density, there's only a big increase for high-speed high-power-density chips with a heavy power grid which takes up a lot of space. Which is...
It's not a must, double-patterned EUV will work fine, just like it does for N3/N2/A16 where there are already a few double-patterned EUV layers.
However if the pitches shrink significantly for A14 the number of DP EUV layers will rise rapidly, and if a single high-NA EUV exposure replaces two...
And N2 isn't much different to N3 really, some pitches are a bit smaller but nothing radical, the main difference is GAA transistors instead of FinFET. Whatever fab technology is good enough for N3 is absolutely fine for N2 and A16, they're all the same process family with addition of first GAA...
That's because pitches are shrinking much more slowly nowadays than suggested by the node names, the area/power improvements are now largely coming from DTCO (things like COAG/PODE/FlexFin/NanoFlex --and special design rules only allowed in carefully-controlled "digital" areas"...) and not so...
If cost for a given functionality is most important not absolute performance/density/power -- which is the case for many *many* products -- then you absolutely don't want to be in a bleeding-edge node, the cost per gate is higher to start off with and they haven't started to slide down the cost...
It's going to be a difficult choice, and could depend on all sorts of things -- do (smaller?) US customers get a higher priority (e.g. faster TAT?) in a US fab, as opposed to playing second fiddle to the likes of Apple in a Taiwanese one? How much priority do they place on security of supply...
It all depends where the biggest markets for the Arizona fab turn out to be -- since the driver for N4C is cost and the Arizona fab is likely to cost more to run than the Taiwan fabs, it might be that N4P/N4X gets more custom. Of course the same fab can make any of them or a mix, so it's not...
