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Search results

  1. I

    Testing the bounds of loyalty for TSMC's inner circle

    It doesn't matter whether you're convinced about whether this is pointless or not, it's how the foundries work -- if you don't do this, you don't get access to the advanced process, so go somewhere else. Oh dear, there isn't anywhere else... :-(
  2. I

    Highest number of pins

    What you describe is usually called "direct drive", it does work over a few cm -- the switch chip packages with CPO are considerably bigger than a chip-only BGA, usually something like 120mm square, but there are issues with integration. Now something called NPO (near-package-optics) is being...
  3. I

    Highest number of pins

    Except I talked to systems companies recently about exactly this approach, and the response was that it was simply too expensive and likely to remain so -- because the longer-range transmitter has to have (electronic) retiming in it (DSP) to avoid the concatenation of losses/eye closure and an...
  4. I

    Highest number of pins

    You can think what you want; the view of many end customers who have to worry about the practicalities is rather different to that of the technology providers like Ranovus who are pushing CPO. Remember how on-board optics were going to take over the world? CPO has even more of the same problems...
  5. I

    Highest number of pins

    The Ranovus solution is exactly what I was describing (and what was used in our feasibility study) -- it needs several cm of in-package tracking not a few mm, and realistically the optics have to be mounted on sockets to allow repairability, which means they need conventional SERDES links not...
  6. I

    Highest number of pins

    There are two uses for CPO in devices like this, one being the short-reach intra-rack or inter-rack (a few m), the other being interconnects across the data centre (up to 2km reach). As currently planned -- or at least, when I was looking at this a year or two ago -- CPO needs an electrical...
  7. I

    Highest number of pins

    It's less heat overall for the system but more heat in the router chip package, which is already stupidly hot -- I've been involved in CPO feasibility studies. Apart from the (solvable) technical problems like fiber attach/connectors, the real problem with CPO is business -- CPO works if you're...
  8. I

    Testing the bounds of loyalty for TSMC's inner circle

    If you want to push the same device through multiple foundries (e.g. TSMC and IFS or Samsung) at advanced nodes, you have no choice except to have separate development teams, because the foundry contracts require that there must be zero chance of any technology leak -- engineers who work on a...
  9. I

    Highest number of pins

    Wow, 10072 pins in a 92.5mm LGA package. Maybe that's why Intel just cancelled the entire Tofino project... :-(
  10. I

    FAKE NEWS: TSMC's 3nm foundry price breaks through $20,000, iPhone 15, GPU price increase

    With TSMC you can get an ultra-super-hot lot -- basically one that is "hand-carried" through the line, everything else has to get out of its way so it never waits for anything -- but there are a *very* limited number of these available per month because they mess up the scheduling and the...
  11. I

    Will Apple become a Medical Power

    The problem with any medical diagnostics by consumer companies like Apple is that they won't 100% focus on making them accurate and reliable because this costs too much money and qualification takes too long, so there will inevitably be false positives (people seeking medical care unnecessarily...
  12. I

    Durations of process steps?

    Come on, use your common sense -- no wafer boats are ever "hand carried" in a modern 300mm fab, all handling is fully automated -- which is why I put quotes around the term... ;-) (so we should also say "tape out"...) What it means is that somebody has to intervene in the automated process...
  13. I

    Durations of process steps?

    I don't know exactly where the time is saved; there are at least two lower (and cheaper) levels of acceleration (e.g. "hot-lot", "super-hot-lot") which are more widely available, I suspect these are speeding up the masks and leapfrogging in the line. The reason given for the high ultra-super-hot...
  14. I

    Durations of process steps?

    Yeah, but if you really *really* need to get samples ASAP it's still "only"*** adds <20% to the 5nm mask costs that you're paying for anyway, so <5% to the total chip NRE cost -- and if it makes the difference between meeting and missing a timescale you've promised to a critical customer... ;-)...
  15. I

    Durations of process steps?

    Not sure, it was a standard lot so presumably 25 or 50 wafers. I don't think the fee depends on this, it's because it "queue-jumps" -- all the other products in the line literally stop to get out of the way of a lot like this -- so the productivity of the entire line drops. For the same reason...
  16. I

    Durations of process steps?

    And what a premium it is -- we recently needed TSMCs ultra-stupid-fast TAT for a 5nm chip, extra cost was $2.5M to get 10 day faster processing... :-(
  17. I

    Nodelets/halfnodes take to their zenith: A new process development model

    I don't think they're all F500 brands, we certainly weren't. The point is that you need a big enough business built on a chip to pay back the development costs, and the best way to do this with advanced processes is to sell an end product, not a chip, and definitely not IP -- as a rule-of-thumb...
  18. I

    Nodelets/halfnodes take to their zenith: A new process development model

    You've hit the nail on the head there, and it's exactly the same reason foundries won't retrofit BSPDN into older nodes -- it makes no business sense (actually, negative...) so they won't do it... ;-) TSMCs current process strategy works extremely well for them, once a process is rolled out...
  19. I

    The viability of CFET alternatives?

    I think it's extremely likely that the EU will stay intact, because (almost) all its members clearly understand they're much better off inside than outside -- especially having seen the effects of the Brexit clusterf*ck, most of the voices who were suggesting leaving have gone strangely quiet...
  20. I

    The viability of CFET alternatives?

    And that's a US-centric view. The world is bigger than the USA... ;-)
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