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ASML and Imec Announce High-NA Lithography Breakthrough

Daniel Nenni

Daniel Nenni

Admin
Staff member
The two companies are collaborating on getting High-NA lithography off the ground and are making solid progress.

By Josh Norem August 9, 2024
Imec High-NA

Credit: Imec

In February, Dutch company ASML announced it had built the world's first High-NA lithography machine. This device would allow finer patterns to be printed onto wafers, paving the way for creating next-generation, sub-2nm transistors. It achieved "first light" two months later in April, and now it's successfully printed both DRAM and logic patterns using the machine, showing the device is working as intended.

Belgium-based Imec is working with ASML in the Netherlands on this project. The two companies are collaborating to get the world's first High-NA lithography machine up and running and have now printed patterns smaller than any existing EUV machine is capable of, demonstrating its readiness for the market. Imec announced the breakthrough in a press release, stating it produced random logic structures down to 9.5nm, typically 13nm, according to Tom's Hardware. This was all done in a single exposure and is suitable for 1.4nm chip production.

ASML Twinscan EXE:5000

The Twinscan EXE:5000 EUV is the world's first High-NA lithography machine, and so far it's looking like it will deliver on its promises. Credit: ASML

Imec also produced random vias at 30nm, 2D structures at 22nm, and DRAM at 32nm, all in a single exposure. Imec notes that a standard EUV machine would require several mask layers, highlighting one of the key benefits of High-NA lithography: its ability to print super-fine patterns with a single exposure. This can reduce the time required to print a wafer, thereby boosting production and allowing for ever-finer patterns to be made for future chips.

The announcement from ASML, which makes the machines, and Imec is essentially a sales pitch to foundries such as TSMC and Samsung, which are still using EUV tools. TSMC is rumored to be holding off on adopting High-NA for now as it's meeting its customers' needs with its current equipment, and adopting all-new lithography machines is a disruptive process that might impact its customers. The machines also cost around $400 million apiece, so that's also an important factor. Samsung is expected to adopt High-NA soon, however.

Despite their steep price tag, Intel is going all-in on High-NA and has reportedly bought all of ASML's High-NA machines for 2024. The company plans on being the first global foundry to put it into production. Intel has said that will happen in 2026 with its Intel 14A node, so it'll be spending this year and next fine-tuning and prepping the machine.

 
The High-NA results for DRAM revealed defects.

imec High-NA demo pillar defects.png
imec High-NA demo DRAM periphery defects.png


With the known central obscuration in the pupil, the ability to pattern multiple patterns simultaneously is compromised in quite a few cases, particularly the variable pitch metal layers including 2D portions.
 
Fred Chen said:
The High-NA results for DRAM revealed defects.

View attachment 2170View attachment 2171

With the known central obscuration in the pupil, the ability to pattern multiple patterns simultaneously is compromised in quite a few cases, particularly the variable pitch metal layers including 2D portions.
Click to expand...
Why does DRAM want wavy 1D lines Fred? As a logic person that looks super bizarre, and based on you not calling it out I assume the wavy-nes is intended rather than some distortion issue.
 
jmlobert said:
Yes, of course, this is a feasibility study. IMEC is and has never been focused on yield, all they need to do is prove that ONE instance works. :) Their fab is not very clean, with respect to gas-phase contamination, they have a much higher tolerance for defects.
Click to expand...
It's not mere contamination because there is pattern dependence.
 
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Fred Chen said:
It's not mere contamination because there is pattern dependence.
Click to expand...
How do you conclude that there is pattern dependence? It seems that in your images there are multiple instances of the same pattern with only a minority of them having the defect.
(sorry if it's a noob question, just trying to learn)
 
kvas said:
How do you conclude that there is pattern dependence? It seems that in your images there are multiple instances of the same pattern with only a minority of them having the defect.
(sorry if it's a noob question, just trying to learn)
Click to expand...
The defects were in the DRAM pattern not the other images. For the 19 nm pitch metal pattern, the only thing I noticed was tip-to-tip "roughness" (some tip-to-tip gaps wider, some narrower). For the 30 nm center-to-center via pattern, the image is not clear enough to judge the shape uniformity, and there is also no known reference to check for missing holes. The 22 nm pitch 2D pattern looked clean, though maybe it is least interesting of the four (not a realistic application). https://www.imec-int.com/en/press/i...dram-structures-using-high-na-euv-lithography
 
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