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2016 Semi Capex & Seasonality trends- 10nm rollout- Multi-Patterning vs. EUV

Robert Maire

Moderator
Tick Tock Tock Tock....WTFOCK?

  • Expected H2 10nm spending ramp may push into Q4
  • Although progressing, EUV HVM still slips out
  • Weak end market demand may crimp volume buys
Most analysts and industry pundits have built up 2016 semiconductor capex spending projections assuming a strong H2 being driven by 3D NAND and 10nm logic/foundry. We are sensing some slippage, particularly on the logic foundry side which may push the ramp start from Q3 into Q4. Capacity related buys could be weaker unless end market demand picks up.

View attachment 16904
Intel officially renounced its Tick Tock strategy on paper in its most recent 10K after the reality of the 10nm delay set in a while ago (which we were first on the street to report..) . At the time it sounded like a unique , one time slip, as the company said it would get back on a two year cadence from the slipped Tick Tock Tock, 3 year cadence of 14nm. That is no longer the case as the company has permanently shifted to a 3 phase cadence "process/architecture/optimization" from "process/architecture" (as graphically publicized in the most recent 10K).

Optimization seems to be code for "milk more out of the huge amount of money you have invested in capex & R&D".

While we think this is the correct approach in the new world of a declining PC market, getting more out of less, the stretching out of two years of capex spend into three years obviously has a negative impact on Intels capex spend and on tool companies.

While process and architecture seem to have a somewhat defined length of time, "optimization" sounds like a very open ended statement akin to saying keep squeezing until no more comes out.

This seems to imply that the next technology node, 10nm or 7nm can be pushed out as far as Intel deems needed rather than introduced on a specific cadence schedule.

While there hasn't been a change in the publicly scheduled H2 2017 roll out of 10nm, we think that Intel can throttle spending to match near term industry conditions.

If this sounds familiar, its what TSMC has been doing forever.

Given that the normally slow Q1 , post partum, post holiday spending downturn was worse than normal this year, particularly in the PC segment , we would not be overly surprised to see Intel back off a bit on capex spending to do "real time" adjustments to capex.

Maybe 10nm remains on time for Intel but perhaps not as fully built out with a lower number of wafer starts based on reduced demand outlook.

We think this adds to the overall risk of the bulk of the 10nm ramp slipping a bit.

TSMC & Samsung soldier on......

TSMC & Samsung seem to be continuing their aggressive pursuit of 10nm. TSMC has Apple demand behind it while Samsung has Qualcomm and internal demand.

As we have pointed out numerous times before , 10nm, or slightly thereafter, continues to look like the intercept point where Intel and TSMC technology cross paths.

Before we get any nasty emails, we would be the first to point out that Intel's 10nm is more advanced than TSMC's 10nm, so its a bit of an apples and oranges comparison.

Tick Tick+....

TSMC at 16nm has had what might be referred a "Tick and Tick+". Essentially two process iterations, a first iteration of 16nm followed by a process tweak of 16nm+.

Using this comparison, its likely that TSMC's 10nm will not equal Intels 10nm but TSMC's 10nm+ might be very comparable. The open question is how quickly with TSMC be able to follow on its initial 10nm offering with its "tweak" of 10nm to catch Intel.

So far spending at both TSMC & Samsung as well as scheduling seems strong but the capacity build out at 10nm could be throttled by the buying response to the Iphone 7 and its "tweaked 16nm" TSMC processor. TSMC is especially good at matching spend to demand.

TSMC's spending timing is much more defined than Intels, because TSMC has to follow the yearly cadence of Apple's September Iphone rollout and has to get 10nm ready for a June ramp in 2017 to build CPU's for the 7S (or whatever it will be called) to be released in September of 2017.

It is amusing to see this "role reversal" as it used to be Intel on a strict Moore's law schedule and TSMC swinging the breeze and now Intel seems open ended with "optimization" while TSMC remains in lockstep with Apples yearly offerings.

Samsung memory side likely more variable
While Samsung's logic side has to "keep up with the Jonses" at 10nm to remain competitive there is likely less pressure on the memory side given Samsung's lead. There is certainly a strong wave of 3D NAND spend but memory pricing is notoriously variable and consumer sensitive.
If there is a place for downside risk at Samsung it will likely be on the memory side.

EUV HVM - like trying to accelerate on an icy road ...

As we had reported from SPIE in February, we were less than impressed by this years reported progress in EUV. While power levels keep improving, the industry only now seems to be seriously looking at the "ecosystem" needed to support HVM. Resists with good line edge roughness, defect free reticle blanks, in situ cleaning, reticle inspection, pellicles and a long list of other bottleneck issues. Not a lot of "closure" on most of these issues (lots of good presentations and papers though...

It was not that long ago that ASML was talking about getting a piece of the 10nm pie for EUV and capturing most all of 7nm. The talk around town now seems to be getting a piece of 7nm and hoping to capture most of 5nm.

Quad patterning is a fore gone conclusion at this point. Back up plans and alternatives for EUV availability seem to be talked about more as a reality than a choice. All the major semiconductor manufacturers were very non-commital about the EUV insertion point deferring to "when its ready".

ASML is still crying all the way to the bank as it still gets to sell a ton of immersion scanners instead. If you want to make a dep & etch salesperson melt in orgasmic bliss, just whisper the words "octo patterning" into their ear. A year or two ago we joked about octo patterning....who will be the first to use it??

KLAC, LRCX & AMAT etc;
Given that metrology and yield management tools are among the first to be bought in a new technology node, KLAC's reported huge order intake should come as no surprise in front of the 10nm wave. Dep and etch tools come later in the 10nm cycle as capacity orders kick in to fill out fab after you get the process down. This is obviously whats expected later in 2016 as the 10nm ramp picks up speed.

As mentioned earlier in this note we think there is a chance of some orders slipping a bit deeper into the year like Q4 but some chip makers, most specifically TSMC likely can't delay much at all.

Pricing related share shifts?

We remain concerned about some share shift from Lam to AMAT on the etch side, as we have mentioned in previous notes, while we think Lam is doing better on their dep side in the near term. We are concerned about AMAT getting aggressive on price to try to gain share and ramp their top line faster even if at the expense of the bottom line.

Obviously market share changes occur mainly at technology node changes (you tend not to lose business once you are designed in) and given that all three semiconductor leaders are changing at a similar timeframe there is opportunity for a lot of share battles.

A bounce off the December bottom....then what??
Its clear from most in the industry that December was pretty much the bottom of business. We have had a nice bounce off the bottom but we don't expect a linear continuation of a similar percentage increase in the next two quarters. More likely flattish to slightly up couple of quarters before we see a sustained ramp late in the year related to 10nm build out.

We would caution that investors could get anxious waiting for the ramp and we could see the stocks pull back once or twice as the market gets nervous especially about macro tech industry trends while waiting for the real ramp.

The other risk is that the ramp is not as big as expected as wafer starts are not built out to expected levels in light of weaker end user demand.

Right now, we maintain that the downside beta is higher than the upside beta as the expectation of a strong H2 ramp has been hyped by most of the sell side. As we have seen over the last five years or so the typically overly bullish predictions of "a ramp in the next half a year" usually haven't panned out as expected only to have ramps pushed out or expectations lowered. We have had some good runs but not nearly as many as most had hoped for or predicted.

Given that this a a more volatile election year and fears on both PC and smart phone sales have increased of late, we would pay close attention to any signs of change in momentum through the year.
 
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Brianhayes

New member
A dreadfully badly written article. Please explain why I should spend hours working out what you mean. Your conclusion refers to the volatility of an election year and suggests I should pay close attention to signs of change.

For God's sake!
 

Robert Maire

Moderator
My newsletter is written with the investor in mind and written with a "Wall St" spin and perspective....not the perspective of a semi professional

A simple summary would be that I think that 10nm may be pushed out a bit later than expected. I am specifically concerned about Intel pushing out further and permanently going to a 3 year cadence as shown in their most recent SEC documents. So its not a one time delay as originally suggested.

Further, EUV continues to slip further out.

Stocks may negatively impacted because most investors are looking for an earlier ramp of 10nm than will actually happen and thus be disappointed, sending the affected stocks downward.

While TSMC may not pass Intel in the first spin of 10nm it may do so at the second, "tweaked version" of 10nm which is closer to Intel specs.

Thats the simplified version......
 

Daniel Nenni

Admin
Staff member
While TSMC may not pass Intel in the first spin of 10nm it may do so at the second, "tweaked version" of 10nm which is closer to Intel specs.
FYI: The second "tweaked" version of TSMC 10nm will be called 7nm and it will be greater than or equal to Intel 10nm specifications. I also believe it will be in HVM before Intel 10nm. By HVM I mean in production outside of the Intel OR R&D facility.

I also believe EUV will go down in semiconductor equipment manufacturing history as one of the biggest product development fails. I see no way for ASML to recoup the amount invested in EUV, not even close. Just my opinion of course.
 
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count

Member
FYI: The second "tweaked" version of TSMC 10nm will be called 7nm and it will be greater than or equal to Intel 7nm specifications. I also believe it will be in HVM before Intel 10nm. By HVM I mean in production outside of the Intel OR R&D facility.

I also believe EUV will go down in semiconductor equipment manufacturing history as one of the biggest product development fails. I see no way for ASML to recoup the amount invested in EUV, not even close. Just my opinion of course.
If TSMC is in high volume production on 7nm before Intel is ramping 10nm, and if TSMC 7nm is equal or better than Intel's 7nm, then TSMC would be 3 years ahead of Intel's current P/A/O roadmap. That would be a disaster for Intel IMO - do you really believe it? I was under the impression that TSMC 7nm would be roughly in line with Intel 10nm.
 

Daniel Nenni

Admin
Staff member
If TSMC is in high volume production on 7nm before Intel is ramping 10nm, and if TSMC 7nm is equal or better than Intel's 7nm, then TSMC would be 3 years ahead of Intel's current P/A/O roadmap. That would be a disaster for Intel IMO - do you really believe it? I was under the impression that TSMC 7nm would be roughly in line with Intel 10nm.
Sorry, that should have been: TSMC 7nm >= Intel 10nm meaning it will perform better than Intel 10nm. TSMC will have the lead with 7nm until Intel comes out with their 7nm. TSMC 10nm will also outperform Intel 14nm in my opinion so they will have the process lead starting in 2H 2017 when the iPhone 7s comes out. Unless of course the next iPad has a 10nm A10x which is certainly possible given that the volumes are a fraction of what the iPhones are and they don't ship until Q1 2017 like the iPad Pro did.

I have my iPad Pro with me this trip and let me tell you Netflix Streaming loves the iPad Pro!
 

Fred Chen

Member
The SPIE papers are now available for download. I checked some key ones by GlobalFoundries (9776-1R) and SK Hynix (9776-1Q). EUV has problems for 7nm and even 10nm design rules. 10nm SADP is already possible by 193i single exposure.
 

Daniel Nenni

Admin
Staff member
The most recent EUV update I have (after SPIE) is not good at all. My bet today would be no EUV at 10nm or 7nm so you have to wonder how Intel will get the smaller feature sizes at 10nm and 7nm to follow Moore's Law and not break the bank on wafer costs? And no way does Intel adopt the TSMC quick node dance steps. Seriously, what will BK do? How long can he delay 10nm and 7nm? And even if Intel does get microprocessors out at 10nm in a reasonable amount of time what about FPGAs, modems, and SoCs?
 

user nl

New member
The most recent EUV update I have (after SPIE) is not good at all. My bet today would be no EUV at 10nm or 7nm ........
DAN, did something bad happen with the newly arrived NXE3350 tools at TSMC? Or is TSMC `throwing up dust` to make things less clear for their competitors?

I understood TSMC's 10 and 7 nm are all scheduled to be done with the same top of the line 193 immersion tools. And in the process of getting 7 nm going they might look/try at some mid node insertion of EUV? But perhaps that is definitely pushed out now? The real EUV HVM was `planned` for TSMC-5 nm node wasn't it?

User nl
 

Daniel Nenni

Admin
Staff member
DAN, did something bad happen with the newly arrived NXE3350 tools at TSMC? Or is TSMC `throwing up dust` to make things less clear for their competitors?

I understood TSMC's 10 and 7 nm are all scheduled to be done with the same top of the line 193 immersion tools. And in the process of getting 7 nm going they might look/try at some mid node insertion of EUV? But perhaps that is definitely pushed out now? The real EUV HVM was `planned` for TSMC-5 nm node wasn't it?

User nl
The most recent EUV update that I was referring to was from the equipment people. I find that they have the most comprehensive view versus a single customer. TSMC presented at SPIE and has stated that they will not use EUV for 10nm or 7nm in HVM and I have no reason to doubt that. 5nm EUV is yet to be determined as I understand it.

According to the equipment people the SPIE EUV presentations this year were "overly kind" to ASML. I can understand ASML customers not wanting to anger ASML but if the emperor has no clothes the investment community should take note. Clearly customers like TSMC, Samsung, and Intel know the truth about EUV and are planning/delaying accordingly.

I'm really looking forward to the Q1 conference calls of the equipment people and Intel. At some point in time they will have to own up to the EUV debacle.
 

user nl

New member
The most recent EUV update that I was referring to was from the equipment people. ......According to the equipment people the SPIE EUV presentations this year were "overly kind" to ASML........
Are these `equipment people` among the top-5 companies (Semiconductor equipment sales leaders by year - Wikipedia, the free encyclopedia) (outside ASML) that have a stake in complex multi-patterning processes that probably will get simpler once EUV gets introduced in HVM?

User nl
 

Robert Maire

Moderator
The continued delay of EUV is obviously good for the likes of Applied, Lam, Tokyo Electron, Hitachi....they get the benefit of multi-patterning which is needed in place of EUV.

The summary from SPIE seems to be that EUV and ASML have slipped another year on EUV...at the last update a year ago, ASML said EUV would get a piece of 10nm and be fully used at 7nm. The current sentiment is that EUV misses 10nm completely and only if very lucky might get a part of late 7nm. The reality at SPIE seemed that most were more focused on EUV at 5nm (maybe...) if everything else in the ecosystem, falls into place.

Per transistor costs are not falling as per Moore's Law and progress has gotten slowed down due to the failure of EUV and the much higher cost of multi patterning...

Because the industry believed what ASML said about EUV, very little effort was spent on alternative technologies that could have worked and the industry was lead down a blind alley...

ASML will obviously never fully recover all the sunk costs on EUV (including the acquisition cost of Cymer) as there aren't that many traditional silicon nodes left....

They still win however, as they fooled the industry into waiting for EUV that never happened while selling immersion systems to those endlessly waiting in line for the promised land of EUV
 

user nl

New member
......as they fooled the industry into waiting for EUV that never happened.......
Interesting to read sometimes how much animosity Martin van den Brink et al. receive from certain 'advisors'. Even though some on 'the Street' may not like that guy, some others in the `Semi neighborhood` seem to respect this guy's accomplishments honoring him with a couple of awards like the one named after the inventor of the integrated circuit...

Never say never....

User nl
 

Fred Chen

Member
Because the industry believed what ASML said about EUV, very little effort was spent on alternative technologies that could have worked and the industry was lead down a blind alley...

ASML will obviously never fully recover all the sunk costs on EUV (including the acquisition cost of Cymer) as there aren't that many traditional silicon nodes left....

They still win however, as they fooled the industry into waiting for EUV that never happened while selling immersion systems to those endlessly waiting in line for the promised land of EUV
Blame the (lack of) competition. Seems no company could make a better product than ASML. Should I mention imprint, ebeam, .... ?
BTW, when I was in the process development side in imec I got more the feeling ASML was pushed heavily in the EUV direction by the big IDMs and foundries and not ASML leading them in the wrong the path (e.g. EUV).
 

benb

Member
This industry has repeatedly rejected process innovations like EUV. In my area I can name ECMP and fixed abrasive CMP. And I would wager other parts of the fab can name similar things. The financial people are in charge now; it is purely a money driven phenomenon. You cannot blame ASML; this industry simply cannot move forward under the present conditions. ASML cannot finish their EUV work because of insufficiency of incentive, and perhaps the macro-economic environment which provides insufficient resources to the chip companies to provide that incentive.

A simpler way to put it: The sharing of economic value between chip company and suppliers has shifted too far away from suppliers, creating short-term profit for the chip companies but in the long run, a deficit in roadmaps which is now reaching criticality.
 

user nl

New member
What some of the experts in the 'neighborhood` think. A nice story from March 17 and 31st by Mark Lapedus:

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Greg McIntyre, director of the Advanced Patterning Department at IMEC; Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries; Uday Mitra, vice president and head of strategy and marketing for the Etch Business Unit and Patterning Module at Applied Materials; Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation.

Part 1:
http://semiengineering.com/where-is-next-gen-lithography/
Part 2: http://semiengineering.com/where-is-next-gen-lithography-2/

User nl
 

user nl

New member
March 28, 2016

EUV Becomes an Answer Instead of a Question

Dramatic Mood Change at SPIE Advanced Litho

by Bryon Moyer
The mood was dramatically different from prior years. Hope was in the air, and there was a distinct sense that the long sought-after achievement might actually be within reach.
If I tell you that the venue for this altered state was the SPIE Advanced Litho conference, then you can probably guess what I’m talking about: EUV. (OK, that and the spoiler title…) The tenor of the presentations, and even comments from the audience, were completely different from last year and prior years.
EUV has been discussed as the next big lithography step since I started my engineering career. With it having started that long ago, you would think that it was far enough in advance to put it in place in time for when it was needed. But it turned out harder than anyone thought, and, instead of EUV, we had things like immersion (for a better effective numerical aperture, or NA) and all the optical correction tricks played so that we can print far smaller features than we really should be able to. Necessity’s maternal nature, and all that.
The last few years have literally held a barely stated question: will EUV even be ready before it’s obsolete? The big focus was on source power, which had been inching up too slowly (with one year reporting something around 50 W and the next year reporting more or less the same number, “only this time we mean it”). But there have been numerous other issues in the way: resists with good exposure and line-edge roughness characteristics; inspection technology; masks and pellicles; the entire ecosystem, really.
This year might be characterized, by contrast, as being a huge sigh of relief. We’re not there yet, but, for the first time, the crowd seemed to have a distinct sense of, “This is going to happen.” That’s a big change. I checked my impression with a few other people, and it wasn’t just my imagination; they agreed.
Past conferences tended to report a few modest bits of progress and then a laundry list of things that still needed working. This year, it was a laundry list of things that work and a dramatically smaller punch list of things to fix. Success isn’t right around the corner, but it finally feels like convergence.


The whole story can be found here:

EUV Becomes an Answer Instead of a Question
 
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user nl

New member
user nl,

If you want the truth about EUV and HVM ask Scotten Jones:

https://www.semiwiki.com/forum/content/author/scotten-jones-7697.html

He is beholden to no one.

D.A.N.
I appreciate very much Scotten's reports and have stated that here on this site. However, there are other sources than SemiWiki, and sometimes the discussions around EUV resemble the discussions among economists about Quantitative Easing and the role of Central Bankers.....It seems to me around the topic of EUV economics, science and politics are fusing and that makes for a heated debate....

Perhaps in 10 years from now some "EUV-historians" (Scotten?) can reflect on this debate by writing "EUV Unleashed: the Origin and Evolution of EUV in Semiconductor Lithography".........

Never waste a good debate and your nice SemiWiki site certainly provides a good platform for this!

User nl
 
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