Intel ex-CEO Gelsinger and his CFO slapped with lawsuit over Intel Foundry disclosures — plaintiffs demand Gelsinger surrenders his entire salary earn

[Artificer60]

Well, here's BK's profile on LinkedIn:

View attachment 2581

And now he is on his way to tanking his 3rd company. I guess Intel's board isn't the only clueless bunch of leeches out there.

 

[BruceA]

I agree with your sentiment -- but Pat being at the State of the Union address sends a pretty powerful message to Intel's employees (and shareholders) that "Intel is important".

Feel free to laugh at me - but it was always a little inspiring to see the current President's portraits at certain defense facilities, especially the ones building the F-22 (I'm old), F-35, etc. They'd often have a "last visited" date to show the local workers that yes, what you're doing is important enough to get the President to fly here and see it.

Obama visited Hillsboro years ago and lots of pictures of that moment when Intel was top dog, LOL

 

[blueone]

Emerald Rappids - 2 Stepping
Granite Rappids( 1 stepping)
Lunar Lake (2 stepping)

Interesting. That would probably make Granite Rapids the first CPU in industry history to be released in one stepping. These CPUs were chiplet designs. Are these stepping counts inclusive of all chiplets? Are you (or whomever came up with the numbers) counting "steppings" by the all-layer variety (letter designations) and metal layer (number) designations, or only the all-layer ones?

 

[nghanayem]

Btw we missed actual work by Pat Gelsinger that went unnoticed

Sapphire Rappids took 8 stepping (should have been out by BK time)
Meteor Lake (4 Stepping)

Emerald Rappids - 2 Stepping
Granite Rappids( 1 stepping)
Lunar Lake (2 stepping)

Source?

 

[Xebec]

Interesting. That would probably make Granite Rapids the first CPU in industry history to be released in one stepping. These CPUs were chiplet designs. Are these stepping counts inclusive of all chiplets? Are you (or whomever came up with the numbers) counting "steppings" by the all-layer variety (letter designations) and metal layer (number) designations, or only the all-layer ones?

MOS 6502 was hand drawn and worked first time ;-) All 3,510 transistors were drawn by hand by BIll Mensch, then engineers cut the mask by hand, and it worked on the first try: https://research.swtch.com/6502

 

[MKWVentures]

Btw we missed actual work by Pat Gelsinger that went unnoticed

Sapphire Rappids took 8 stepping (should have been out by BK time)
Meteor Lake (4 Stepping)

Emerald Rappids - 2 Stepping
Granite Rappids( 1 stepping)
Lunar Lake (2 stepping)

full steppings? or does that include mask revisions (A-2) . How many mask revisions were done (dash stepping)

Granite rapids literally changed nodes, was delayed and was enhanced (according to Pat)

 

[MKWVentures]

MOS 6502 was hand drawn and worked first time ;-) All 3,510 transistors were drawn by hand by BIll Mensch, then engineers cut the mask by hand, and it worked on the first try: https://research.swtch.com/6502

Shockley had no tapeouts on the Bell Labs transistor.... Those guys did it right the first time

 

[blueone]

MOS 6502 was hand drawn and worked first time ;-) All 3,510 transistors were drawn by hand by BIll Mensch, then engineers cut the mask by hand, and it worked on the first try: https://research.swtch.com/6502

I love being proven wrong!

 

[siliconbruh999]

Source?

Data from CPUID in Linux

SPR - https://openbenchmarking.org/s/Intel+Xeon+Platinum+8490H
EMR - https://openbenchmarking.org/s/INTEL+XEON+PLATINUM+8592
GNR - https://openbenchmarking.org/s/Intel+Xeon+6980P

You can search for stepping in the link here are the screenshot

full steppings? or does that include mask revisions (A-2) . Home many mask revisions were done (dash stepping)

Granite rapid literally changes nodes, was delayed and was enhanced (according to Pat)

There may have mask revisions like A1/A2 it's what reported in Software by the CPU unless Intel is programming false data in this I don't see a reason this is wrong.

as for GNR delayed and enhanced you can delay the silicon before tape out i can't answer for sure though cause i don't work at Intel and neither i am PG

 

[ai268]

Shockley had no tapeouts on the Bell Labs transistor.... Those guys did it right the first time

It was just like programming 40-50 years ago. You wrote the program on the pieces of paper first, checked the syntax and program logic again and again. Then punched the cards, input the program and got the printout result. Hope it was right at the first time.