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intel 3 Roadmap

H

hskuo

Well-known member
Good link!. 10% density improvement also vs. Intel 4:

“In summary, Intel 3 technology provides the ultimate family of FinFET process nodes and delivers a full generation of performance and 10% better density than the Intel 4 node. The Intel 3 node reached manufacturing readiness in the fourth quarter of 2023 and is now in high-volume manufacturing for the Intel Xeon 6 processor family“
 
For me the coolest part is how they went into detail what they changed to get the results they did. It lets the uninformed in chip design know what sort of things happen to make these sub-nodes beyond "just" rounding out the process corners to lower variation for better perf/power at a product level.

The one thing that I didn't see coming was the 18% freq @iso power being the 2 fin device rather than the 3 fin device. 18% is almost an intel 7 -> intel 4 improvement, and is tied with 10nm Super Fin for the largest single intranode improvement intel (and maybe any logic firm for that matter) has ever done. But having the HD cell achieve that freq improvement vs the HP cell is IMO really impressive.

Eyeballing the power at 0.65V there seems to be a maybe ~25% ARM core power reduction with a freq bump, an ~40% power reduction at 3.1GHz, and an ~60% power reduction at 3.6 GHz. Intel also quoted a 5x leakage reduction vs intel 4. My device physics is a bit rusty, but I don't really know how they came up with the last number. Ioff is "only" 2.5x lower on intel 3. Does Ioff not directly equal leakage? Put another way, is leakage usually quoted as off power rather than off current?

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Xebec said:
Good link!. 10% density improvement also vs. Intel 4:

“In summary, Intel 3 technology provides the ultimate family of FinFET process nodes and delivers a full generation of performance and 10% better density than the Intel 4 node. The Intel 3 node reached manufacturing readiness in the fourth quarter of 2023 and is now in high-volume manufacturing for the Intel Xeon 6 processor family“
Click to expand...

I certainly have more trust in a conference paper, well done. Is the Intel Xeon processor family chiplet based? Or are they full chip? I would really like to see some full chip numbers.
 
Daniel Nenni said:
I certainly have more trust in a conference paper, well done. Is the Intel Xeon processor family chiplet based? Or are they full chip?
Click to expand...
Yes but it has to be, full chip looks to easily be more than 800mm2.
Daniel Nenni said:
I would really like to see some full chip numbers.
Click to expand...
You won’t ever see it from intel it would seem. But considering that mtl on intel 4 already had MIM, on-die voltage regulators, power gating, three SRAM bitcells, 8VTs, and the analog necessary for a die to die phy. Intel 4 only really seemed to be missing the HD logic cell. Now that there are HD cells, TSV support, and intel mentioning Xeon6 has the high speed DDR5 phy on the large cpu die; I don’t see why you couldn’t design a monolithic SOC as long as you don’t need native 5V or deep implants. This hypothetical chip would obviously be less sophisticated than a wave 3 QCOM SOC with an integrated radio, or some high voltage large die Broadcom networking chip. But you should be able to go more sophisticated (from a process/supported device level) than what you would do on a lead product A series SOCs (ie no MIM, no HP cells/multiple CPPs, no high V, sub 100mm2 die, no uLVT, high SRAM content).
 
Daniel Nenni said:
I certainly have more trust in a conference paper, well done. Is the Intel Xeon processor family chiplet based? Or are they full chip? I would really like to see some full chip numbers.
Click to expand...
They are chiplet IO die on Intel 7 and CPU on Intel 3 hot chips xeon also the die size for SRF Intel 3 chiplet with 144c is 578mm2 feels too big but still smaller than EMR Die ~700mm2
 
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nghanayem said:
Does Ioff not directly equal leakage? Put another way, is leakage usually quoted as off power rather than off current?
Click to expand...
Semantics. Look at the quote, they state "at same drive current" so the Ioff that has a 5x improvement is not the one at same VDD but the one at at the VDD that gives the same Ion as Intel 4. Vg should be 0 in all cases as that is the voltage at which is the gate of the transistor leaking in an inverter.
 
Daniel Nenni said:
I certainly have more trust in a conference paper, well done. Is the Intel Xeon processor family chiplet based? Or are they full chip? I would really like to see some full chip numbers.
Click to expand...

FWIW, The Xeon 6 product shipping now (Sierra Forest) has 3 dice; 2 I/O and the compute die (middle).

The compute die has 144 e-cores and 108MB of cache, so it’s pretty big. A couple of Google searches have it in the 578-588mm2 range.


1718800163275.png
 
SPQR54 said:
Semantics. Look at the quote, they state "at same drive current" so the Ioff that has a 5x improvement is not the one at same VDD but the one at at the VDD that gives the same Ion as Intel 4. Vg should be 0 in all cases as that is the voltage at which is the gate of the transistor leaking in an inverter.
Click to expand...
But it looks like there is no significant increase in drive current at a given Vdd based on those Idd-Vdd curves? My interpretation was that the width had decreased, so 2.5X decrease in leakage current/width and 2x decrease in width. Not completely clear though.
 
are there sierra forest servers for sale? Is there sierra forest in public for doing teardown?
The wafer starts on Intel4 and Intel3 are still very low... does Intel plan to have a foundry customer soon.
 
MKWVentures said:
are there sierra forest servers for sale?
Click to expand...
At the last earnings they said that they were shipping for revenue to their first customer, and at computex they launched it for ROW. Folks have already reviewed them and checking supermicro’s site they have a few skus that folks can buy.
MKWVentures said:
Is there sierra forest in public for doing teardown?
Click to expand...
Considering it just launched in standalone form, no. My guess is it won’t be too long until techinsights gets their hands on one (assuming they prioritize actually tearing one down over all the other things launching).
MKWVentures said:
The wafer starts on Intel4 and Intel3 are still very low...
Click to expand...
That’s mostly a Bob Swan and a disag problem. 40M 40mm2 MTL dies is not a whole lot of wafers. By direct comparison 40M 250mm2 RPL dies is more than 6x as many wafers. As for sever products filling the fab just look at AMD. Even a product of unquestioned leadership like Genoa with huge hyperscaller momentum only crossed over with the prior gen Milan CPUs this quarter (well over a year after it released). Data center products seem to take a long time to move through the pipeline.
MKWVentures said:
does Intel plan to have a foundry customer soon.
Click to expand...
They already have a “$4B edge customer”.

EDIT: My bad I went to fact check myself and I misremembered the quote. The $4B was a composite of the i16 MTK deal + the intel 3 datacenter and edge deal + the few hundred million in packaging deals they had back in early 2023. Definitely less impressive, but even if we conservatively say we are “only” talking $1-2B, that is a meaningful contract.
 
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MKWVentures said:
Is there a takeaway on how this compares to TSMC N3...... Is @Scotten Jones doing an article on VLSI ?
Click to expand...
Would love his opinion. My less discerning eye says this sits squarely between N3E and N4P on a PPA basis. HD logic density same as N4P. HP density is much better than N4P and very close to N3/E. Both TSMC nodes likely win by a a very wide margin when it comes to characteristics mobile APs like (such as switching energy). And on the other side of things, Intel 4/3 have a MIM cap that is generations ahead of all other logic firms. TSMC also like half a node of an SRAM density lead on the N5/N3/N3E families. Considering that intel 4 perf/watt seemingly is splitting hairs with N4P in HPC scenarios, the fact that SRF can frequently beat Zen4 EPYC efficiency despite the inferior core arch, and I think it is fair to say intel 3 far exceeds N4P in that metric. Beyond that it is hard to say if it is at the level of N3E/P. Considering that intel said that the leader's best node in 2024 (which presumably means N3E) was about equal to intel 3 for perf/watt, I think it is safe to assume i3 at the very least isn't better.

The one oddity is the HD logic lib performance. I would not be shocked if you told me that little beast of a transistor had more performance than the minimum sheet width N2 transistor. Of course you would have higher power consumption and area, but I can't stop marveling at how fast that 210 is. I mean the N3E 2-1 is by TSMC's numbers the same speed as N4P's HD lib at iso power. Versus the N4P HP lib it would be slower, but that is totally fine (and expected) because you are getting lower area and less power. For the i3 210h to be that much faster than the i4 240h at same power while effective device width is reduced by 33% is simply insane. It's a shame intel CPU designers seem to rarely use HD libs. In a funny way it seems like AMD's products (which seem to only use HD cells but with uLVT/MIM/overdrive to hit high freq instead of relying on tall cells) would benefit from intel 3 more than intel's own products. :LOL:
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