No, TSMC's 0.07um2 cell is single fin for each transistor. Intel's 0.0706um2 cell is 3 fins for pull down. SRAM area is easy to calculate:
For the densest cell, each PD, PG, and PU has a single fin. That's total of 4 active fins. Assuming you print fins at constant pitch and remove every other fin for isolation, densest SRAM needs 8 fins. So area is 8 FP x 2 CPP. This gives 0.069um2 for TSMC and 0.047um2 for Intel. In reality other ground rules or considerations such as desire to have a close gear ratio to metal pitch, makes the cell a bit bigger. You can of course print the fins directly at the desired spacing as opposed to printing at constant pitch and removing every other fin to get smaller cells, but I am not aware of anyone practicing it.
The next cell would be 2 fins for PD. Roughly 0.086um2 for TSMC (which is actually comparable to their dense cell at 20nm) and 0.0588 um2 for Intel. Next would be if you use 3 fins for PD and that gives 0.104um2 for TSMC and 0.0706um2 for Intel.
So a fair comparison is between Intel's 0.0499um2 cell and TSMC's 0.07um2. Of course Intel did not use their smallest cell in product (same story at 22nm).
