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DATE: Wednesday, September 10, 2025 TIME: 8:00am PDT | 11:00am EDT | 3:00pm GMT | 8:30pm IST In mission-critical sectors like aerospace, defense, and space systems, reliability is everything. Failures carry enormous risk, making rigorous design validation essential. This webinar explores how advanced PSpice simulation techniques using Monte Carlo and worst-case analysis can help engineers evaluate statistical …
Date: Tuesday, September 16, 2025 Time: 10:00 BST / 11:00 CEST / 12:00 EEST / 14:30 IST In the high-stakes world of aerospace and defense (A&D), engineers face mounting challenges in designing …
This webinar explores strategies for optimizing SMT filter designs, addressing spurious responses, parasitic behaviors, and PCB layout challenges using Cadence’s Microwave Office and Modelithics simulation models to ensure accurate and …
Speaker: Soo Chuan Tang, Principal Application Engineer 10:00am~11:00am Next-Generation Spectre FX FastSPICE Simulator and Spectre X Integration with GPU 11:00am~11:15am Q&A Description: Leveraging a FastSPICE engine built from the ground …
Overview Join us for a series of expert-led webinars showcasing cutting-edge simulation and analysis tools—from RF/mmWave modeling to advanced thermal and electromagnetic solutions. While designed for a broad range of high-performance electronics applications, each session also highlights how these technologies can be adapted to meet the rigorous demands of aerospace and defense (A&D) systems. Topics …
Speaker: Hong-Cheang Quek, AE Director 10:00am~11:00am iPegasus Verification System for Virtuoso Studio 11:00am~11:15am Q&A Description: Today's complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle turnaround time, bridge a demand gap, and improve productivity between custom implementation and physical verification tools, Cadence …
Speaker: Kee Tat Ong, Principal Application Engineer 10:00am~11:00am Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure 11:00am~11:15am Q&A Description: With more designs migrating to advanced process nodes, chips are getting smaller, but design complexity is increasing in order to deliver better power, performance, or area. These optimizations are restricted by the time window to …
