CadenceTECHTALK: Next-generation Spectre FX FastSPICE Simulator and Spectre X Integration with GPU

Online

Speaker: Soo Chuan Tang, Principal Application Engineer 10:00am~11:00am Next-Generation Spectre FX FastSPICE Simulator and Spectre X Integration with GPU 11:00am~11:15am Q&A Description: Leveraging a FastSPICE engine built from the ground …

Cloud Tech Day 2025

Hyatt Regency Santa Clara 5101 Great America Pkwy, Santa Clara, CA, United States

Join industry leaders and Cadence cloud experts at this free must-attend Cloud event of the year to explore the latest cloud EDA innovations, share ideas, and grow your professional connections. All attendees …

CadenceCONNECT: Jasper User Group 2025

San Jose Convention Center 150 W San Carlos St, San Jose, CA, United States

CadenceCONNECT: Jasper User Group 2025 is October 29 and 30 in San Jose, CA. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and methodologies. The Jasper User Group Conference is the premier …

CadenceTECHTALK: iPegasus Verification System for Virtuoso Studio

Online

Speaker: Hong-Cheang Quek, AE Director 10:00am~11:00am iPegasus Verification System for Virtuoso Studio 11:00am~11:15am Q&A Description: Today's complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle turnaround time, bridge a demand gap, and improve productivity between custom implementation and physical verification tools, Cadence …

CadenceTECHTALK: Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure

Online

Speaker: Kee Tat Ong, Principal Application Engineer 10:00am~11:00am Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure 11:00am~11:15am Q&A Description: With more designs migrating to advanced process nodes, chips are getting smaller, but design complexity is increasing in order to deliver better power, performance, or area. These optimizations are restricted by the time window to …

Chiplet Summit 2026

Santa Clara Convention Center Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States

All the Solutions for Developing Chiplets 2025 Keynote Addresses from Industry Leaders: Alphawave Semi, Arm, Cadence Design Systems, Keysight, Open Compute Project, Synopsys, Teradyne 2025’s Main Topics Included: AI/ML Acceleration, Open Chiplet Economy, Advanced Packaging Methods, Die-to-die Interfaces, Working with Foundries signup to be a 2026 SPONSOR / Exhibitor REGISTER HERE