CadenceCONNECT: Jasper User Group 2025 is October 29 and 30 in San Jose, CA. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world …
Speaker: Hong-Cheang Quek, AE Director 10:00am~11:00am iPegasus Verification System for Virtuoso Studio 11:00am~11:15am Q&A Description: Today's complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle turnaround time, bridge a demand gap, and improve productivity between custom implementation and physical verification tools, Cadence …
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Speaker: Kee Tat Ong, Principal Application Engineer 10:00am~11:00am Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure 11:00am~11:15am Q&A Description: With more designs migrating to advanced process nodes, chips are getting smaller, but design complexity is increasing in order to deliver better power, performance, or area. These optimizations are restricted by the time window to …
All the Solutions for Developing Chiplets 2025 Keynote Addresses from Industry Leaders: Alphawave Semi, Arm, Cadence Design Systems, Keysight, Open Compute Project, Synopsys, Teradyne 2025’s Main Topics Included: AI/ML Acceleration, Open Chiplet Economy, Advanced Packaging Methods, Die-to-die Interfaces, Working with Foundries signup to be a 2026 SPONSOR / Exhibitor REGISTER HERE
