The 2025 International Conference on Computer-Aided Design Call For Papers Jointly sponsored by IEEE and ACM, IEEE ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, …
CadenceCONNECT: Jasper User Group 2025 is October 29 and 30 in San Jose, CA. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world …
As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift …
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for …
October 29, 2025 - 11:00 AM EST October 30, 2025 – 10:00 AM JST/KST Discover the 5 Critical Memory Market Trends Reshaping Semiconductors in 2026 AI workloads, HBM4 adoption, and …
Continue reading "Webinar: 5 Expectations for the Memory Market in 2026"
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. The industry as a whole has gotten to this point of incredible complexity through the process of countless …
Strengthen your knowledge and skills by learning about new packaging technologies in Fan-in, Fan-out WLP, Embedded packaging technology, System on Chip (SOC), System in Package (SiP), 3D IC, WLP, TSV, …
Scaling Together in a Dynamic World The photonic chip industry is reaching new heights - but scaling production, applications, and investments requires a united effort. As demand surges for high-speed, …
Connect to the embedded community With its 20 years of history and experience in Europe, embedded world is the most professional and largest exhibition in its field, and has accumulated …
November 4, 2025 | 10:00 AM PST This webinar will present advanced simulation tools and techniques for the design of GaN power amplifiers with increased assurance of stable operation that …
Details Imaging radar has rapidly evolved into a critical technology for autonomous systems, with patent activity accelerating significantly over the past decade. From 2015 to 2024, global imaging radar patent …
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to …
Continue reading "Webinar: HLV – Formal Verification of Synthesizable C++/SystemC Designs"
