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The library I created to match publicized Intel 4 rules but without help of PDK, so it was just for fun. I did around 25 primitives ranging from NAND/NOR up to full adder. FWIW 6 tracks, one of which was power worked easily, only the most complex cells needed to go above M1, so routing between...
OK, but my information came originally from end users who just counted the days until their chips came back after tapeout. The calendar delay is all they care about.
NAND layers are uniform and featureless, not individually masked. That is their economic (and yield) advantage. They stop every 100 layers or so to add a stabilizing pattern which keeps the vertical etch from drifting on very tall stacks,
There is some conventional CMOS underneath, probably...
I know it is possible to get the masks made very rapidly. A couple of days delay, and they can pipeline mask production in order of need. Again, for some cost of displacing other work.
I'm pretty sure it is nothing close to 100 masks. Would be fascinated to see data / authoritative blog...
Thanks!
I did find some notes on SHL for automotive chips that halved the process time in 2021 but those parts were in a process with only 2 months normal.
I am assured that a month is still possible for major customers on important lots, but it seems like the amount of disruption to do that...
Previously the fastest hot lots I found on a leading-edge process are around 30 to 40 days faster than a normal schedule. Now I heard that ultra-hot lots exist which make the journey in a month (80 to 90 days faster than regular).
Is that real? On a 5nm process or below?
There appears to be no clear information on Panther Lake, and certainly 3 tiles are in the running. You do not need 3D to eliminate the need for advanced IO circuits. 2.5D interfaces can also be done with a single IO phy design for ultrashort throw which is much less complex than a full IO...
Assuming it would be 18A there is zero chance of them having all the IO needed by an Apple chip on that process. Look how Intel plan to use 18A on their own chips, the 18A is purely logic and then the IO (and SRAM) is on a Intel3 substrate. In principle that could interest Apple but the...
Inferencing is where other designs give Nvidia the closest run for the money. Models can be optimized and run in fairly predictable ways. CoT runs multiple inferences. Nvidia GPUs lead in flexibility and the maturity of the software to do new things, so they are the leaders in training the...
Not quite. It is not binary compatibility. Nvidia builds new compilation for each generation, and apps are recompiled or even retuned for each generation.
The beauty or ugliness of that is just how difficult it is to get a GPU running at full speed. The computation elements are tiny compared...
The pitch shrink anemia is partly because they still use an SRAM circuit that made sense in the planar era and seem never to have changed that. The planar design depended upon variable strength transistors and when translated into FinFET ended up with a design that was 2 rails high and needed a...
Eva has been around many decades, long enough to be full grown just like United. Does it force older staff to retire?
I expect Intel to be professional and provide a great service, if their senior management enables it.
Exactly. And when Moore wrote the original article scaling was unknown (Carver Mead had worked out a complex set of rules, but Dennard had not yet distilled the MOS core out of it), and many of the packages in his examples used multiple devices (chiplets) inside one can. So Dennard scaling...
The movement of production for 3 out of Oregon just to Ireland looks like a right-sizing of Intel 3 resources clearing the decks for faster execution on 18A.
