Early SoC Dynamic Power Analysis Needs Hardware Emulation

Early SoC Dynamic Power Analysis Needs Hardware Emulation
by Lauro Rizzatti on 04-16-2024 at 6:00 am

Early SoC Dynamic Power Analysis Figure 1
The relentless pursuit for maximizing performance in semiconductor development is now matched by the crucial need to minimize energy consumption.

Traditional simulation-based power analysis methods face insurmountable challenges to accurately capture complex designs activities in real-world scenarios. As the scale… Read More


On-the-Fly Code Checking Catches Bugs Earlier

On-the-Fly Code Checking Catches Bugs Earlier
by Synopsys on 08-10-2021 at 6:00 am

Euclide GUI

There’s no question that chip designs are getting more complex, driven by the power, performance, and area (PPA) demands of applications like artificial intelligence (AI), automotive, and cloud computing. This complexity, of course, trickles down to the design and testbench code. When engineers can find and fix bugs before… Read More